How to Precisely Erase Data in 3D NAND Flash Memory
This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed.
Original patent title: “Erasing and erasing verification for three-dimensional NAND memory”
This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed. Granted to Yangtze Memory Technologies Co in 2024 with 23 claims, and it is expected to expire in 2042.
Coverage
What does this patent actually cover?
This patent details a method for erasing memory cells in a 3D NAND device more precisely. First, a relatively large "first erase voltage" is applied and gradually increased by a "first erase step voltage" until the memory cells pass an "initial erase verification" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). This is a coarse erase. After this initial pass, the system performs several "sub-erase verifications" using different "sub-erase verification voltages" to check the erase state more closely (Claim 1, Claim 6). Based on whether the cells pass or fail these sub-verifications, a "second erase voltage" is applied. This second voltage is increased by a much smaller "second erase step voltage," which is dynamically adjusted by the sub-verification results (Claim 1, Claim 9). This fine-tuning ensures a more accurate and complete erase. For example, if a cell is almost erased but not quite, the sub-verifications help determine the exact small voltage boost needed.
The gap
What does this patent NOT cover?
- Does not cover erase methods that do not use an initial coarse erase step followed by a finer, adaptively adjusted erase step.
- Does not cover memory erase processes for types of memory other than 3D NAND, such as DRAM or NOR flash.
- Does not cover erase verification methods that do not involve incrementally increasing an erase voltage in two distinct stages with different step sizes.
- Does not cover methods where the second erase step voltage is not determined by the results of intermediate sub-erase verifications.
- Does not cover memory devices that do not have a control circuit configured to perform these specific erase and verification steps.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The clever part is the two-stage erase process with adaptive fine-tuning. It uses a larger voltage step for initial erasing, then switches to much smaller, dynamically adjusted voltage steps based on detailed sub-verifications. This allows for a precise erase without wasting cycles or overstressing the memory cells.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Solid-state drives (SSDs) in computers
Smartphones and tablets with internal storage
USB flash drives
Enterprise data center storage arrays
Memory cards for cameras and other devices
Why it matters
The bigger picture
NAND flash memory is crucial for storing data in many devices, from smartphones to data centers. Efficient and reliable erasing is vital for memory longevity and performance. This method aims to prevent over-erasing, which can damage cells, and under-erasing, which leaves residual data. By fine-tuning the erase process, it helps extend the lifespan of 3D NAND memory and improve its reliability.
Filed
September 22, 2022
Granted
November 12, 2024
Market context
Who's building on this
Companies in this space
Companies involved in manufacturing 3D NAND flash memory, such as Yangtze Memory Technologies Co Ltd (YMTC), Samsung, SK Hynix, Micron, and Kioxia (formerly Toshiba Memory), are continually developing and refining erase and programming algorithms. These companies invest heavily in optimizing memory performance and longevity, often incorporating techniques similar to those described to improve their products.
Market impact
The development of more efficient and reliable erase methods directly impacts the performance and cost-effectiveness of NAND flash memory. Improvements like this can lead to longer-lasting SSDs and other storage devices, reducing warranty claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more → and improving user experience. It also allows for higher density memory by ensuring cells can be reliably erased and reprogrammed more times, which is crucial for the ever-growing demand for data storage.
Claim 1 — Plain English
What this patent covers
This patent details a method for erasing memory cells in a 3D NAND device more precisely. First, a relatively large "first erase voltage" is applied and gradually increased by a "first erase step voltage" until the memory cells pass an "initial erase verification" (Claim 1). This is a coarse erase. After this initial pass, the system performs several "sub-erase verifications" using different "sub-erase verification voltages" to check the erase state more closely (Claim 1, Claim 6). Based on whether the cells pass or fail these sub-verifications, a "second erase voltage" is applied. This second voltage is increased by a much smaller "second erase step voltage," which is dynamically adjusted by the sub-verification results (Claim 1, Claim 9). This fine-tuning ensures a more accurate and complete erase. For example, if a cell is almost erased but not quite, the sub-verifications help determine the exact small voltage boost needed.
The clever bit
The clever part is the two-stage erase process with adaptive fine-tuning. It uses a larger voltage step for initial erasing, then switches to much smaller, dynamically adjusted voltage steps based on detailed sub-verifications. This allows for a precise erase without wasting cycles or overstressing the memory cells.
What it does not cover
- Does not cover erase methods that do not use an initial coarse erase step followed by a finer, adaptively adjusted erase step.
- Does not cover memory erase processes for types of memory other than 3D NAND, such as DRAM or NOR flash.
- Does not cover erase verification methods that do not involve incrementally increasing an erase voltage in two distinct stages with different step sizes.
- Does not cover methods where the second erase step voltage is not determined by the results of intermediate sub-erase verifications.
- Does not cover memory devices that do not have a control circuit configured to perform these specific erase and verification steps.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
15/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
20/20
Granted within 5 years
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$29K – $94K
Midpoint $59K · 16.0 yr remaining · industry ×1.5
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
23 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Huang, K. (2024). How to Precisely Erase Data in 3D NAND Flash Memory (U.S. Patent No. 12,142,328). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
Embed
Add this patent to your site
Drop this plain-English patent card into any blog post or article — free, no signup. It always links back to the full breakdown here.
<div data-patentlens-widget data-patent-number="US12142328"></div> <script src="https://patentbrief.org/embed.js" async></script>
Stay in the loop
Get a weekly digest of new patents.
One email per week. No spam. Unsubscribe anytime.
Keep exploring
Related patents you should know
US 4683195 · 1987
How to Make Billions of Copies of a DNA Segment
This patent describes the Polymerase Chain Reaction (PCR), a method to rapidly create many copies of a specific piece of DNA or RNA, enabling its detection and analysis.
Cetus Corp
US 8697359 · 2014
How to Edit Genes in Human Cells Using an Engineered CRISPR System
This patent describes an engineered CRISPR-Cas9 system for precisely cutting DNA in eukaryotic cells to change how genes work, opening the door for gene editing in complex organisms.
Massachusetts Institute of Technology
US 7657849 · 2010
How the iPhone's Slide-to-Unlock Gesture Works
Apple's 2010 patent describes unlocking a device by dragging a specific graphical image across the touchscreen along a predefined path, a gesture that became iconic with the original iPhone.
Apple Inc
US 4733665 · 1988
How Doctors Implant a Permanent Stent Using a Balloon
This patent describes the method for placing a permanent, expandable wire mesh tube inside a blood vessel or other body tube using a balloon-tipped catheter to widen it and keep it open.
Expandable Grafts Partnership
US 4965188 · 1990
How to Make Many Copies of a DNA Piece with Heat
This patent describes the Polymerase Chain Reaction (PCR) method, a technique to make millions of copies of a specific DNA segment using a heat-resistant enzyme and repeated temperature changes.
Cetus Corp
US 4235871 · 1980
How to Encapsulate Active Materials in Lipid Bubbles Efficiently
This patent describes a method for trapping biologically active substances inside tiny, multi-layered fat bubbles called liposomes, using a specific water-in-oil emulsion and gel-forming process to improve how much material gets captured.
Individual
Semantically similar
You might also find these interesting
US 9947413 · 2018 · Seoul National University R&DB Foundation
How to Program 3D Layered Memory Chips More Precisely
US 9685235 · 2017 · Seoul National University R&DB Foundation
How to Prepare 3D Flash Memory for Use
US 9263111 · 2016 · Micron Technology
How 3D Memory Chips Fix Tiny Flaws to Keep Working
US 4531203 · 1985 · Tokyo Shibaura Electric Co Ltd
How Flash Memory Cells Use an Erase Gate to Clear Data
More to explore
More in Semiconductors & Chips
US 5563422 · 1996 · Nichia Chemical Industries Ltd
How Nichia Created the First Practical Blue LED Electrodes
US 10373050 · 2019 · Qualcomm Inc
How to Make AI Run Faster on Smaller Computer Chips
US 2981877 · 1961 · Fairchild Semiconductor Corp
How Robert Noyce Invented the Modern Integrated Circuit
US 2569347 · 1951 · Bell Telephone Laboratories Inc
The Invention of the Junction Transistor
New to patents?
Common Questions
Frequently Asked Questions
What does How to Precisely Erase Data in 3D NAND Flash Memory cover?
This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed.
Who owns patent US 12142328?
Yangtze Memory Technologies Co owns this patent, granted in 2024.
When does this patent expire?
This patent is expected to expire on September 22, 2042, when the invention enters the public domain.
What problem does this patent solve?
NAND flash memory is crucial for storing data in many devices, from smartphones to data centers. Efficient and reliable erasing is vital for memory longevity and performance. This method aims to prevent over-erasing, which can damage cells, and under-erasing, which leaves residual data. By fine-tuning the erase process, it helps extend the lifespan of 3D NAND memory and improve its reliability.
What does this patent NOT cover?
Does not cover erase methods that do not use an initial coarse erase step followed by a finer, adaptively adjusted erase step.
Same assignee
More from Yangtze Memory Technologies Co
Patent monitoring