How 3D Memory Chips Fix Tiny Flaws to Keep Working
Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip.
Original patent title: “Sub-block disabling in 3D memory”
Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. Granted to Micron Technology in 2016 with 21 claims and 2 forward citations, and it is expected to expire in 2035.
Coverage
What does this patent actually cover?
This patent describes a system and method for selectively disabling small, defective parts of a 3D memory chip, called "sub-blocks," to improve manufacturing yield and device longevity. The apparatus includes a "sub-block disabling circuit" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1) that stores the addresses of known defective sub-blocks. When the memory receives a request for an address, this circuit checks if the requested address matches a stored defective one. If there's a match, the circuit disables access to that specific sub-block, for example, by deactivating its "drain select gate (SGD) driver" (Claim 2). The patent also covers methods where, if a "threshold number" of sub-blocks in a larger "block" are defective, the entire block might be disabled (Claim 9), or only the individual defective sub-blocks if the count is below the threshold (Claim 13). For example, if a tiny section of a 3D NAND flash chip fails during manufacturing, this system can mark that specific sub-block as unusable, allowing the rest of the chip to function normally.
The gap
What does this patent NOT cover?
- Does not cover disabling entire memory blocks unless a specific threshold of sub-block defects within that block is met (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 9).
- Does not cover memory devices that are not organized into "blocks" containing "two or more sub-blocks" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover memory repair mechanisms that physically re-route data to redundant memory cells instead of just disabling access.
- Does not cover disabling defective memory cells at a granularity finer than a "sub-block" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover disabling sub-blocks in a 2D memory architecture, as it specifically mentions "three-dimensional NOT AND (NAND) memory device" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 6) and "different tier of a semiconductor construction" (Claim 4).
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The noveltynoveltyThe requirement that an invention be different from anything publicly known before its priority date.Read more → lies in the granular, address-based disabling of specific "sub-blocks" within a 3D memory structure, rather than just whole blocks or relying on more complex physical remapping. By using a content-addressable memory (CAM) to quickly identify and disable defective sub-blocks, the system can efficiently bypass small flaws without impacting the performance of the rest of the memory.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Solid-state drives (SSDs)
USB flash drives
Memory cards (SD cards, microSD cards)
Embedded flash memory in smartphones and tablets
Enterprise storage arrays
Data center storage
Why it matters
The bigger picture
Modern 3D NAND flash memory chips are incredibly complex, stacking billions of memory cells in layers. Manufacturing defects are inevitable. This patent provides a crucial mechanism for salvaging chips with minor flaws, significantly improving manufacturing yield and reducing waste. By allowing memory devices to operate even with some defective parts, it helps lower costs and increase the availability of high-capacity storage solutions. This approach is fundamental to the economic viability of large-scale 3D NAND production.
Filed
April 9, 2015
Granted
February 16, 2016
Market context
Who's building on this
Companies in this space
Micron Technology, as the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, continues to be a major player in 3D NAND development and manufacturing. Other leading 3D NAND producers like Samsung, Kioxia (formerly Toshiba Memory), Western Digital, and SK Hynix also employ similar defect management strategies to maximize yield and reliability in their high-density flash memory products.
Market impact
This type of defect management capability is critical for the mass production of high-density 3D NAND flash memory. It enables manufacturers to produce usable chips even with minor imperfections, which directly impacts the cost-effectiveness and availability of SSDs and other flash-based storage. Without such mechanisms, manufacturing yields would be significantly lower, driving up costs and limiting the growth of the flash memory market.
Claim 1 — Plain English
What this patent covers
This patent describes a system and method for selectively disabling small, defective parts of a 3D memory chip, called "sub-blocks," to improve manufacturing yield and device longevity. The apparatus includes a "sub-block disabling circuit" (Claim 1) that stores the addresses of known defective sub-blocks. When the memory receives a request for an address, this circuit checks if the requested address matches a stored defective one. If there's a match, the circuit disables access to that specific sub-block, for example, by deactivating its "drain select gate (SGD) driver" (Claim 2). The patent also covers methods where, if a "threshold number" of sub-blocks in a larger "block" are defective, the entire block might be disabled (Claim 9), or only the individual defective sub-blocks if the count is below the threshold (Claim 13). For example, if a tiny section of a 3D NAND flash chip fails during manufacturing, this system can mark that specific sub-block as unusable, allowing the rest of the chip to function normally.
The clever bit
The novelty lies in the granular, address-based disabling of specific "sub-blocks" within a 3D memory structure, rather than just whole blocks or relying on more complex physical remapping. By using a content-addressable memory (CAM) to quickly identify and disable defective sub-blocks, the system can efficiently bypass small flaws without impacting the performance of the rest of the memory.
What it does not cover
- Does not cover disabling entire memory blocks unless a specific threshold of sub-block defects within that block is met (Claim 9).
- Does not cover memory devices that are not organized into "blocks" containing "two or more sub-blocks" (Claim 1).
- Does not cover memory repair mechanisms that physically re-route data to redundant memory cells instead of just disabling access.
- Does not cover disabling defective memory cells at a granularity finer than a "sub-block" (Claim 1).
- Does not cover disabling sub-blocks in a 2D memory architecture, as it specifically mentions "three-dimensional NOT AND (NAND) memory device" (Claim 6) and "different tier of a semiconductor construction" (Claim 4).
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
10/40
Early citations
Claim breadth
14/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
5/20
Granted 10–20 years ago
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$73K – $234K
Midpoint $146K · 8.5 yr remaining · industry ×1.5
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
21 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Ha, C. W. (2016). How 3D Memory Chips Fix Tiny Flaws to Keep Working (U.S. Patent No. 9,263,111). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How 3D Memory Chips Fix Tiny Flaws to Keep Working cover?
Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip.
Who owns patent US 9263111?
Micron Technology owns this patent, granted in 2016.
When does this patent expire?
This patent is expected to expire on April 9, 2035, when the invention enters the public domain.
What is patent US 9263111 cited by?
This patent has been cited by 2 later patents that build on its ideas.
What problem does this patent solve?
Modern 3D NAND flash memory chips are incredibly complex, stacking billions of memory cells in layers. Manufacturing defects are inevitable. This patent provides a crucial mechanism for salvaging chips with minor flaws, significantly improving manufacturing yield and reducing waste. By allowing memory devices to operate even with some defective parts, it helps lower costs and increase the availability of high-capacity storage solutions. This approach is fundamental to the economic viability of large-scale 3D NAND production.
What does this patent NOT cover?
Does not cover disabling entire memory blocks unless a specific threshold of sub-block defects within that block is met (Claim 9).
Patent monitoring