How to Program 3D Layered Memory Chips More Precisely
This patent describes a method for precisely programming the control transistors and memory cells in advanced 3D non-volatile memory chips, ensuring reliable data storage in stacked layers.
Original patent title: “Method of initializing and programming 3D non-volatile memory device”
This patent describes a method for precisely programming the control transistors and memory cells in advanced 3D non-volatile memory chips, ensuring reliable data storage in stacked layers. Granted to Seoul National University R&DB Foundation in 2018 with 26 claims, and it is expected to expire in 2036.
Coverage
What does this patent actually cover?
This patent details a method for setting up and programming 3D non-volatile memory devices, which are like tiny, layered data storage cities. First, it applies a specific voltage (a "first program voltage") to a "selected string selection line" (a control wire) in a chosen memory layer (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). Then, it checks if the "string selection transistors" (SSTs, which are like gates for memory strings) connected to that wire have reached a target "threshold voltage" (the voltage needed to turn them on). This check identifies which SSTs are already "programmed" and which are "unprogrammed" (Claim 1). Next, it programs the actual "memory cell transistors" (MCTs) within the memory strings that are coupled with the *programmed* SSTs. These MCTs are set to a specific threshold voltage so they can function as "screening transistors" (Claim 1). Finally, it uses these newly programmed MCTs to block programming to the channel lines of the *programmed* SSTs, while a "third program voltage" is applied to the selected string selection line to *selectively program* only the *unprogrammed* SSTs (Claim 1). This ensures precise control over which parts of the memory are programmed.
The gap
What does this patent NOT cover?
- Does not cover programming methods for traditional 2D (planar) non-volatile memory structures.
- Does not cover programming string selection transistors without an intermediate verification step to distinguish programmed from unprogrammed ones.
- Does not cover programming memory cell transistors without using them as screening transistors for subsequent string selection transistor programming.
- Does not cover memory architectures that do not include distinct string selection lines, wordlines, and channel lines in a 3D arrangement.
- Does not cover programming techniques that do not involve applying a first, second, and third program voltage in the specified sequence.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The noveltynoveltyThe requirement that an invention be different from anything publicly known before its priority date.Read more → lies in the two-stage programming of string selection transistors, specifically by using *already programmed memory cell transistors* as "screening transistors" to selectively block programming for certain paths while allowing others. This allows for more precise and controlled programming of the complex 3D stacked memory architecture.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Solid-state drives (SSDs)
Smartphone internal storage (eMMC, UFS)
USB flash drives
Enterprise data center storage
Memory cards (SD cards, microSD cards)
3D NAND flash memory chips
Why it matters
The bigger picture
3D non-volatile memory, often called 3D NAND, is the backbone of modern data storage, found in solid-state drives (SSDs), smartphones, and data centers. As memory chips become denser by stacking layers, precise control over programming individual cells and their control transistors is critical. This method aims to improve the reliability and efficiency of these complex 3D structures, which directly impacts the performance and lifespan of storage devices.
Filed
November 3, 2016
Granted
April 17, 2018
Market context
Who's building on this
Companies in this space
Major 3D NAND manufacturers like Samsung, SK Hynix, Micron, Kioxia (formerly Toshiba Memory), and Western Digital are continuously developing and refining programming methods for their advanced memory chips. Research institutions and universities, like the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more → Seoul National University R&DB Foundation, contribute fundamental advancements in this field.
Market impact
This type of patent contributes to the ongoing evolution of 3D non-volatile memory technology, enabling higher densities, better performance, and improved reliability for NAND flash products. Advancements in programming methods directly impact the cost-effectiveness and competitive landscape for solid-state drives and other storage solutions, allowing for continued scaling of storage capacity in consumer and enterprise markets.
Claim 1 — Plain English
What this patent covers
This patent details a method for setting up and programming 3D non-volatile memory devices, which are like tiny, layered data storage cities. First, it applies a specific voltage (a "first program voltage") to a "selected string selection line" (a control wire) in a chosen memory layer (Claim 1). Then, it checks if the "string selection transistors" (SSTs, which are like gates for memory strings) connected to that wire have reached a target "threshold voltage" (the voltage needed to turn them on). This check identifies which SSTs are already "programmed" and which are "unprogrammed" (Claim 1). Next, it programs the actual "memory cell transistors" (MCTs) within the memory strings that are coupled with the *programmed* SSTs. These MCTs are set to a specific threshold voltage so they can function as "screening transistors" (Claim 1). Finally, it uses these newly programmed MCTs to block programming to the channel lines of the *programmed* SSTs, while a "third program voltage" is applied to the selected string selection line to *selectively program* only the *unprogrammed* SSTs (Claim 1). This ensures precise control over which parts of the memory are programmed.
The clever bit
The novelty lies in the two-stage programming of string selection transistors, specifically by using *already programmed memory cell transistors* as "screening transistors" to selectively block programming for certain paths while allowing others. This allows for more precise and controlled programming of the complex 3D stacked memory architecture.
What it does not cover
- Does not cover programming methods for traditional 2D (planar) non-volatile memory structures.
- Does not cover programming string selection transistors without an intermediate verification step to distinguish programmed from unprogrammed ones.
- Does not cover programming memory cell transistors without using them as screening transistors for subsequent string selection transistor programming.
- Does not cover memory architectures that do not include distinct string selection lines, wordlines, and channel lines in a 3D arrangement.
- Does not cover programming techniques that do not involve applying a first, second, and third program voltage in the specified sequence.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
17/20
Very broad protection
Recency
10/20
Granted 5–10 years ago
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$24K – $78K
Midpoint $49K · 10.1 yr remaining · industry ×1.5
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
26 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
KWON, D. W., Park, B. G., Lee, S. H., & KIM, D. B. (2018). How to Program 3D Layered Memory Chips More Precisely (U.S. Patent No. 9,947,413). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/9947413/method-of-initializing-and-programming-3d-non-volatile-memory-device
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How to Program 3D Layered Memory Chips More Precisely cover?
This patent describes a method for precisely programming the control transistors and memory cells in advanced 3D non-volatile memory chips, ensuring reliable data storage in stacked layers.
Who owns patent US 9947413?
Seoul National University R&DB Foundation owns this patent, granted in 2018.
When does this patent expire?
This patent is expected to expire on November 3, 2036, when the invention enters the public domain.
What problem does this patent solve?
3D non-volatile memory, often called 3D NAND, is the backbone of modern data storage, found in solid-state drives (SSDs), smartphones, and data centers. As memory chips become denser by stacking layers, precise control over programming individual cells and their control transistors is critical. This method aims to improve the reliability and efficiency of these complex 3D structures, which directly impacts the performance and lifespan of storage devices.
What does this patent NOT cover?
Does not cover programming methods for traditional 2D (planar) non-volatile memory structures.
Same assignee
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