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How Multi-Level Cell Memory Stores More Data in Less Space

Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming.

Granted 1999ExpiredExpired 2017Owned by Toshiba CorpInvented by Tomoharu Tanaka, Ken Takeuchi

Original patent title: “Semiconductor device and memory system

Plain-English explanation by SahiLast reviewed · June 13, 2026

Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming. Granted to Toshiba Corp in 1999 with 64 claims and 326 forward citations, and it is now in the public domain.

Coverage

What does this patent actually cover?

This patent details a technique for Multi-Level Cell (MLC) flash memory, where each memory cell can store more than one bit of data by using multiple distinct voltage thresholds. It describes a two-step programming process where the voltage bias applied to the cell increases in specific, controlled increments (ΔVpp1 and ΔVpp2). By using a smaller step-up value for the first programming phase and a larger one for the second, the device ensures the threshold voltage distributions remain accurate and distinct, allowing the cell to reliably hold values like '1', '2', or '3'.

The gap

What does this patent NOT cover?

  • Does not cover Single-Level Cell (SLC) memory where each cell stores only one bit.
  • Does not cover memory architectures that do not use stepwise bias increases for programming.
  • Does not cover the physical manufacturing process of the silicon wafers themselves.
  • Does not cover the specific error-correction algorithms used to read the data.

These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.

Key facts

Patent numberUS 5903495
StatusExpired
FieldSemiconductors & Chips
AssigneeToshiba Corp
InventorsTomoharu Tanaka, Ken Takeuchi
Filed1997
Granted1999
Expires2017 (expired)
Claims64
Times cited326
LitigationNone on record
Value · $90K$288KModest

What made this novel

The innovation lies in using different step-up voltage increments (ΔVpp1 < ΔVpp2) for different stages of the programming cycle to maintain tight control over the voltage thresholds, preventing data overlap in high-density memory.

The Patent Drawing

Representative patent drawing for Semiconductor device and memory system (US 5903495)
Representative figure · US 5903495All figures on Google Patents →
Semiconductor device and memor…(Primary claim)semiconductorsconsumer electronics

Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.

Where you've seen this

Real-world examples

01

NAND flash memory chips

02

Solid State Drives (SSDs)

03

SD cards and microSD cards

04

Embedded flash memory in smartphones

Why it matters

The bigger picture

This technology is a foundational element of modern high-capacity flash storage. By allowing a single cell to represent multiple states, it enabled the transition from expensive, low-capacity storage to the dense NAND flash memory found in every smartphone, SSD, and USB drive today.

Filed

March 17, 1997

Granted

May 11, 1999

Market context

Who's building on this

Companies in this space

Toshiba (now Kioxia) remains a major player in this space. Other industry giants like Samsung, Micron, and SK Hynix have built upon these fundamental principles to develop even denser technologies like TLC (Triple-Level Cell) and QLC (Quad-Level Cell) memory.

Market impact

This patent helped trigger the shift toward high-density flash storage, effectively lowering the cost per gigabyte of memory. It became a critical piece of the intellectual property landscape that allowed the flash memory industry to scale up to the terabyte-level capacities common in modern computing.

Claim 1 — Plain English

What this patent covers

This patent details a technique for Multi-Level Cell (MLC) flash memory, where each memory cell can store more than one bit of data by using multiple distinct voltage thresholds. It describes a two-step programming process where the voltage bias applied to the cell increases in specific, controlled increments (ΔVpp1 and ΔVpp2). By using a smaller step-up value for the first programming phase and a larger one for the second, the device ensures the threshold voltage distributions remain accurate and distinct, allowing the cell to reliably hold values like '1', '2', or '3'.

The clever bit

The innovation lies in using different step-up voltage increments (ΔVpp1 < ΔVpp2) for different stages of the programming cycle to maintain tight control over the voltage thresholds, preventing data overlap in high-density memory.

What it does not cover

  • Does not cover Single-Level Cell (SLC) memory where each cell stores only one bit.
  • Does not cover memory architectures that do not use stepwise bias increases for programming.
  • Does not cover the physical manufacturing process of the silicon wafers themselves.
  • Does not cover the specific error-correction algorithms used to read the data.

Patent timeline

Filing

Application submitted to the patent office

Publication

Application published, typically 18 months after filing

Grant

Patent officially issued

Expiration

Patent enters public domain

This patent is in the public domain

See the Freedom to Build guide — what is free to use, what is not, and how to cite this patent.

View guide →

PatentBrief Score

Impact Score

Strong

Citation count

40/40

Highly cited

Claim breadth

20/20

Very broad protection

Recency

0/20

Older than 20 years

Assignee scale

0/20

Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →

PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.

Heuristic Value Estimate

What this patent might be worth

Modest

$90K$288K

Midpoint $180K · expired or expiring · industry ×1.5

Adjust inputs →

Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.

Patent Claims

0 independent claims · 1 dependent

Claims are the legal boundaries of the patent. An independent claim stands alone. A dependent claim adds limitations to its parent, narrowing — but not broadening — the scope.

The original legal language

Original claims

64 claims as filed with the patent office.

Concepts involved

ClaimPrior artNon-obviousnessNoveltySpecificationAssigneePatent term

Citations

Patent lineage

Cites earlier patents

4

earlier patents this invention cites as foundations

View prior art →

Cited by later patents

326

later patents that build on this invention

View patents →

Cite this patent

Tanaka, T., & Takeuchi, K. (1999). How Multi-Level Cell Memory Stores More Data in Less Space (U.S. Patent No. 5,903,495). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system

Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.

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Common Questions

Frequently Asked Questions

What does How Multi-Level Cell Memory Stores More Data in Less Space cover?

Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming.

Who owns patent US 5903495?

Toshiba Corp owns this patent, granted in 1999.

When does this patent expire?

This patent has expired and is now in the public domain — anyone can use the invention freely.

What is patent US 5903495 cited by?

This patent has been cited by 326 later patents that build on its ideas.

What problem does this patent solve?

This technology is a foundational element of modern high-capacity flash storage. By allowing a single cell to represent multiple states, it enabled the transition from expensive, low-capacity storage to the dense NAND flash memory found in every smartphone, SSD, and USB drive today.

What does this patent NOT cover?

Does not cover Single-Level Cell (SLC) memory where each cell stores only one bit.

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Last reviewed: June 13, 2026 · PatentBrief is not a law firm and this is not legal advice.