How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate
This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip.
Original patent title: “Microelectronic package for wafer-level chip scale packaging with fan-out”
This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip. Granted to Invensas in 2019 with 7 claims and 13 forward citations, and it is expected to expire in 2036.
Coverage
What does this patent actually cover?
ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1 describes a 'package-on-package device' that uses a 'metal substrate' with distinct 'outer conductive pads' and 'inner conductive pads'. A 'microelectronic device' connects to the 'inner conductive pads' via 'first interconnects', which can be 'posts' (Claim 4). 'Wire bond wires' attach to the 'outer conductive pads'. A 'redistribution layer' on the lower surface connects these pads. The key feature is that the 'outer conductive pads are located outside of a perimeter of the microelectronic device for the fan-out from the inner conductive pads located below the microelectronic device' (Claim 1). This allows connections to spread out beyond the chip's footprint. For example, a processor chip could be connected to memory chips stacked above it, with all connections efficiently routed to a larger circuit board below.
The gap
What does this patent NOT cover?
- Does not cover chip packages that do not use a metal substrate as the base (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover single-chip packages; it specifically claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more → a 'package-on-package device' (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover packaging where electrical connections do not 'fan-out' beyond the microelectronic device's perimeter (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover packages that connect chips without using both 'wire bond wires' and 'first interconnects' (posts) as described (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1, 4).
- Does not cover packages without a 'redistribution layer' connecting the pads on the lower surface (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The noveltynoveltyThe requirement that an invention be different from anything publicly known before its priority date.Read more → lies in combining a metal substrate with electrically isolated inner and outer conductive pads, specifically designed for a 'package-on-package' configuration. This setup allows for efficient 'fan-out' of connections from both wire bonds and stacked chips, maximizing connectivity in a minimal footprint.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Smartphones
Wearable electronics
Internet of Things (IoT) devices
High-density memory modules
Automotive electronics control units
Why it matters
The bigger picture
This technology is crucial for making smaller, more powerful electronic devices. By enabling the stacking of multiple chips (like a processor and memory) in a 'package-on-package' arrangement, it saves valuable space inside devices. The 'fan-out' capability allows for more electrical connections in a compact area, which is essential for high-performance chips in modern smartphones, wearables, and other miniaturized electronics.
Filed
October 24, 2016
Granted
January 15, 2019
Market context
Who's building on this
Companies in this space
Invensas LLC, the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, is part of Xperi Corporation, which actively licenses its semiconductor packaging technologies. Major semiconductor manufacturers and packaging service providers like TSMC, Amkor Technology, ASE Group, and Samsung Electronics are continuously developing and utilizing advanced packaging techniques, including fan-out and package-on-package solutions, for their high-performance and compact electronic products.
Market impact
This patent contributes to the intellectual property landscape for advanced microelectronic packaging, a field critical for the ongoing miniaturization and performance enhancement of electronic devices. Technologies like wafer-level chip scale packaging with fan-out have become essential for enabling the compact designs and high functionality seen in modern mobile phones, smartwatches, and other portable electronics, potentially influencing design choices and licensing agreements in the industry.
Claim 1 — Plain English
What this patent covers
Claim 1 describes a 'package-on-package device' that uses a 'metal substrate' with distinct 'outer conductive pads' and 'inner conductive pads'. A 'microelectronic device' connects to the 'inner conductive pads' via 'first interconnects', which can be 'posts' (Claim 4). 'Wire bond wires' attach to the 'outer conductive pads'. A 'redistribution layer' on the lower surface connects these pads. The key feature is that the 'outer conductive pads are located outside of a perimeter of the microelectronic device for the fan-out from the inner conductive pads located below the microelectronic device' (Claim 1). This allows connections to spread out beyond the chip's footprint. For example, a processor chip could be connected to memory chips stacked above it, with all connections efficiently routed to a larger circuit board below.
The clever bit
The novelty lies in combining a metal substrate with electrically isolated inner and outer conductive pads, specifically designed for a 'package-on-package' configuration. This setup allows for efficient 'fan-out' of connections from both wire bonds and stacked chips, maximizing connectivity in a minimal footprint.
What it does not cover
- Does not cover chip packages that do not use a metal substrate as the base (Claim 1).
- Does not cover single-chip packages; it specifically claims a 'package-on-package device' (Claim 1).
- Does not cover packaging where electrical connections do not 'fan-out' beyond the microelectronic device's perimeter (Claim 1).
- Does not cover packages that connect chips without using both 'wire bond wires' and 'first interconnects' (posts) as described (Claim 1, 4).
- Does not cover packages without a 'redistribution layer' connecting the pads on the lower surface (Claim 1).
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
23/40
Moderately cited
Claim breadth
5/20
Moderate scope
Recency
10/20
Granted 5–10 years ago
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$84K – $269K
Midpoint $168K · 10.0 yr remaining · industry ×1.4
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
7 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Katkar, R., & Prabhu, A. S. (2019). How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate (U.S. Patent No. 10,181,457). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/10181457/microelectronic-package-for-wafer-level-chip-scale-packaging-with-fan-out
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate cover?
This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip.
Who owns patent US 10181457?
Invensas owns this patent, granted in 2019.
When does this patent expire?
This patent is expected to expire on October 24, 2036, when the invention enters the public domain.
What is patent US 10181457 cited by?
This patent has been cited by 13 later patents that build on its ideas.
What problem does this patent solve?
This technology is crucial for making smaller, more powerful electronic devices. By enabling the stacking of multiple chips (like a processor and memory) in a 'package-on-package' arrangement, it saves valuable space inside devices. The 'fan-out' capability allows for more electrical connections in a compact area, which is essential for high-performance chips in modern smartphones, wearables, and other miniaturized electronics.
What does this patent NOT cover?
Does not cover chip packages that do not use a metal substrate as the base (Claim 1).
Patent monitoring