How Chips Are Stacked and Wired in Tiny Phone Parts
MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones.
Original patent title: “Package-on-package with fan-out WLCSP”
MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones. Granted to MediaTek in 2012 with 28 claims and 14 forward citations, and it is expected to expire in 2031.
Coverage
What does this patent actually cover?
This patent describes a way to build a "package-on-package" (PoP) or "system-in-package" (SiP) that stacks different types of computer chips efficiently. It uses a "package carrier" (like a small circuit board) where a main "semiconductor die" (a chip, like a processor) is attached face-down (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). Between this chip and the carrier is a "rewiring laminate structure" (Claim 1) that takes the tiny electrical connections from the chip's surface and "re-routes" them to "fan-out bond pads" (Claim 5) that extend beyond the edge of the chip (Claim 1). This makes the connections easier to access. On top of this, another "IC package" (like a memory chip) is mounted on the same carrier, partially overlapping the first chip (Claim 1). This stacking allows multiple chips to fit into a very small area. For example, a phone's baseband chip could be the bottom die, with a DRAM chip stacked above it (Claim 7).
The gap
What does this patent NOT cover?
- Does not cover chip stacking where the upper IC package directly touches the lower semiconductor die (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 2).
- Does not cover arrangements where the re-routed metal layer does not extend beyond the edge of the semiconductor die (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover packages where the IC package and the semiconductor die are not at least partially overlapped (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover systems where the rewiring laminate structure is absent, or where connections are made directly from the die's contact pads without re-routing (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1, 5).
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The noveltynoveltyThe requirement that an invention be different from anything publicly known before its priority date.Read more → lies in combining a "package-on-package" structure with a "fan-out wafer level chip scale package" (WLCSP) for the bottom die. This "rewiring laminate structure" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1) extends connections beyond the die's edge (Claim 1), allowing for more connection points and easier integration with the stacked IC package, all while keeping the overall footprint small.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Smartphones
Wearable devices
Tablet computers
Internet of Things (IoT) devices
System-in-package (SiP) modules
Why it matters
The bigger picture
This packaging method helps make electronic devices smaller and more powerful by allowing different chips to be stacked closely together. By using a "fan-out" wiring technique, it creates more connection points around the chip, which can improve electrical performance and reduce the overall size of the component. This is crucial for compact devices like smartphones and wearables that need many functions in a tiny space.
Filed
October 25, 2011
Granted
November 13, 2012
Market context
Who's building on this
Companies in this space
Companies like MediaTek, Qualcomm, Intel, and Samsung are major players in designing and manufacturing integrated circuits and advanced packaging solutions for mobile and consumer electronics. Semiconductor foundries such as TSMC and ASE Group also continuously develop and refine packaging technologies, including various forms of PoP and SiP, to meet the demands for smaller, more powerful devices.
Market impact
This patent contributed to the ongoing trend of miniaturization and integration in consumer electronics. By enabling more efficient stacking of diverse chips like processors and memory within a single module, it helped reduce the physical footprint of components. This allowed for thinner and smaller devices, particularly in the smartphone and wearable markets, by making high-density integration more feasible and cost-effective.
Claim 1 — Plain English
What this patent covers
This patent describes a way to build a "package-on-package" (PoP) or "system-in-package" (SiP) that stacks different types of computer chips efficiently. It uses a "package carrier" (like a small circuit board) where a main "semiconductor die" (a chip, like a processor) is attached face-down (Claim 1). Between this chip and the carrier is a "rewiring laminate structure" (Claim 1) that takes the tiny electrical connections from the chip's surface and "re-routes" them to "fan-out bond pads" (Claim 5) that extend beyond the edge of the chip (Claim 1). This makes the connections easier to access. On top of this, another "IC package" (like a memory chip) is mounted on the same carrier, partially overlapping the first chip (Claim 1). This stacking allows multiple chips to fit into a very small area. For example, a phone's baseband chip could be the bottom die, with a DRAM chip stacked above it (Claim 7).
The clever bit
The novelty lies in combining a "package-on-package" structure with a "fan-out wafer level chip scale package" (WLCSP) for the bottom die. This "rewiring laminate structure" (Claim 1) extends connections beyond the die's edge (Claim 1), allowing for more connection points and easier integration with the stacked IC package, all while keeping the overall footprint small.
What it does not cover
- Does not cover chip stacking where the upper IC package directly touches the lower semiconductor die (Claim 2).
- Does not cover arrangements where the re-routed metal layer does not extend beyond the edge of the semiconductor die (Claim 1).
- Does not cover packages where the IC package and the semiconductor die are not at least partially overlapped (Claim 1).
- Does not cover systems where the rewiring laminate structure is absent, or where connections are made directly from the die's contact pads without re-routing (Claim 1, 5).
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Moderate
Citation count
23/40
Moderately cited
Claim breadth
19/20
Very broad protection
Recency
5/20
Granted 10–20 years ago
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$76K – $245K
Midpoint $153K · 5.2 yr remaining · industry ×1.4
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Patent Claims
0 independent claims · 1 dependent
Claims are the legal boundaries of the patent. An independent claim stands alone. A dependent claim adds limitations to its parent, narrowing — but not broadening — the scope.
The original legal language
Original claims
28 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Chen, N., & Hsu, C. (2012). How Chips Are Stacked and Wired in Tiny Phone Parts (U.S. Patent No. 8,310,051). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/8310051/package-on-package-with-fan-out-wlcsp
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How Chips Are Stacked and Wired in Tiny Phone Parts cover?
MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones.
Who owns patent US 8310051?
MediaTek owns this patent, granted in 2012.
When does this patent expire?
This patent is expected to expire on October 25, 2031, when the invention enters the public domain.
What is patent US 8310051 cited by?
This patent has been cited by 14 later patents that build on its ideas.
What problem does this patent solve?
This packaging method helps make electronic devices smaller and more powerful by allowing different chips to be stacked closely together. By using a "fan-out" wiring technique, it creates more connection points around the chip, which can improve electrical performance and reduce the overall size of the component. This is crucial for compact devices like smartphones and wearables that need many functions in a tiny space.
What does this patent NOT cover?
Does not cover chip stacking where the upper IC package directly touches the lower semiconductor die (Claim 2).
Patent monitoring