How Chips Are Stacked and Wired in Tiny Phone Parts

MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones.

What it covers

This patent describes a way to build a "package-on-package" (PoP) or "system-in-package" (SiP) that stacks different types of computer chips efficiently. It uses a "package carrier" (like a small circuit board) where a main "semiconductor die" (a chip, like a processor) is attached face-down (Claim 1). Between this chip and the carrier is a "rewiring laminate structure" (Claim 1) that takes the tiny electrical connections from the chip's surface and "re-routes" them to "fan-out bond pads" (Claim 5) that extend beyond the edge of the chip (Claim 1). This makes the connections easier to access. On top of this, another "IC package" (like a memory chip) is mounted on the same carrier, partially overlapping the first chip (Claim 1). This stacking allows multiple chips to fit into a very small area. For example, a phone's baseband chip could be the bottom die, with a DRAM chip stacked above it (Claim 7).

What it doesn't cover

• —Does not cover chip stacking where the upper IC package directly touches the lower semiconductor die (Claim 2).
• —Does not cover arrangements where the re-routed metal layer does not extend beyond the edge of the semiconductor die (Claim 1).
• —Does not cover packages where the IC package and the semiconductor die are not at least partially overlapped (Claim 1).
• —Does not cover systems where the rewiring laminate structure is absent, or where connections are made directly from the die's contact pads without re-routing (Claim 1, 5).

The clever bit

The novelty lies in combining a "package-on-package" structure with a "fan-out wafer level chip scale package" (WLCSP) for the bottom die. This "rewiring laminate structure" (Claim 1) extends connections beyond the die's edge (Claim 1), allowing for more connection points and easier integration with the stacked IC package, all while keeping the overall footprint small.

Why it matters

This packaging method helps make electronic devices smaller and more powerful by allowing different chips to be stacked closely together. By using a "fan-out" wiring technique, it creates more connection points around the chip, which can improve electrical performance and reduce the overall size of the component. This is crucial for compact devices like smartphones and wearables that need many functions in a tiny space.

Real-world examples

• 1.Smartphones
• 2.Wearable devices
• 3.Tablet computers
• 4.Internet of Things (IoT) devices
• 5.System-in-package (SiP) modules