Stacking Chips with Light-Guiding Plastic Wires
TSMC's patent describes a method for building advanced chip packages that combine electrical and light-based circuits using polymer waveguides and an integrated fan-out redistribution layer for faster communication.
Original patent title: “Structures and process flow for integrated photonic-electric ic package by using polymer waveguide”
TSMC's patent describes a method for building advanced chip packages that combine electrical and light-based circuits using polymer waveguides and an integrated fan-out redistribution layer for faster communication. Granted to Taiwan Semiconductor Manufacturing Co TSMC in 2024 with 23 claims, and it is expected to expire in 2043.
Coverage
What does this patent actually cover?
This patent details a method for constructing a silicon photonic (SiPh) structure by integrating electrical and optical components. First, a Photonic Integrated Circuit (PIC) is attached on top of an Electrical Integrated Circuit (EIC) (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). Next, a layer containing one or more Polymer Waveguides (PWGs) is formed and positioned on top of the PIC (Claim 1). These PWGs are structured with a core layer made of a first polymer and at least two cladding layers made of a second polymer that surrounds the core (Claim 4), acting like tiny light pipes. An Integrated Fan-Out Redistribution Layer (InFO RDL) is then formed on top of the PWG layer, and optical lenses are created adjacent to the InFO RDL to direct light signals through it (Claim 1). For example, a light signal from an external source could be directed by an optical lens, coupled into a PWG via a SiPh grating coupler (Claim 6), travel through the polymer waveguide, and then be directed into the PIC, enabling high-speed optical communication within the chip package.
The gap
What does this patent NOT cover?
- Does not cover optical interconnections that use glass fibers or other non-polymer materials for waveguides.
- Does not cover chip packages where the photonic integrated circuit is not placed directly on top of the electrical integrated circuit.
- Does not cover optical signal routing without an Integrated Fan-Out Redistribution Layer (InFO RDL) positioned on top of the polymer waveguides.
- Does not cover systems where light signals are not directed by an optical lens adjacent to the InFO RDL layer.
- Does not cover purely electrical connections between stacked chips without the use of optical waveguides.
- Does not cover waveguide structures that do not consist of a core layer surrounded by at least two cladding layers of different polymers.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The noveltynoveltyThe requirement that an invention be different from anything publicly known before its priority date.Read more → lies in precisely stacking electrical and photonic integrated circuits with polymer waveguides and an integrated fan-out redistribution layer, enabling efficient optical communication directly within a compact chip package. This allows light to carry data between different chip layers, overcoming the speed and power limits of traditional electrical connections.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
High-performance computing chips
AI accelerator chips
Data center network switches
Advanced chip packaging for servers
Future generations of smartphone processors requiring higher bandwidth
Why it matters
The bigger picture
As computer chips become more powerful, the electrical wires connecting different parts of the chip struggle to keep up with the speed and amount of data. This patent offers a way to use light, which is much faster, to transmit data within a chip package. By integrating optical and electrical components closely, it helps overcome these bottlenecks, which is crucial for high-performance computing, artificial intelligence accelerators, and data centers.
Filed
August 9, 2023
Granted
December 31, 2024
Market context
Who's building on this
Companies in this space
Taiwan Semiconductor Manufacturing Co (TSMC), the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, is a leading global semiconductor foundry and is actively developing advanced packaging technologies like this. Other major chip manufacturers and foundries, such as Intel and Samsung, are also investing heavily in similar integrated photonic-electronic packaging solutions to meet the demands of high-bandwidth applications like AI and data centers.
Market impact
This patent addresses a critical need in the semiconductor industry to overcome the limitations of electrical interconnects, especially for high-bandwidth and low-power communication. Its successful implementation could enable a new generation of high-performance processors and accelerators, potentially becoming a standard for advanced chip packaging. This could lead to more powerful and energy-efficient devices, particularly in the rapidly growing fields of artificial intelligence and cloud computing.
Claim 1 — Plain English
What this patent covers
This patent details a method for constructing a silicon photonic (SiPh) structure by integrating electrical and optical components. First, a Photonic Integrated Circuit (PIC) is attached on top of an Electrical Integrated Circuit (EIC) (Claim 1). Next, a layer containing one or more Polymer Waveguides (PWGs) is formed and positioned on top of the PIC (Claim 1). These PWGs are structured with a core layer made of a first polymer and at least two cladding layers made of a second polymer that surrounds the core (Claim 4), acting like tiny light pipes. An Integrated Fan-Out Redistribution Layer (InFO RDL) is then formed on top of the PWG layer, and optical lenses are created adjacent to the InFO RDL to direct light signals through it (Claim 1). For example, a light signal from an external source could be directed by an optical lens, coupled into a PWG via a SiPh grating coupler (Claim 6), travel through the polymer waveguide, and then be directed into the PIC, enabling high-speed optical communication within the chip package.
The clever bit
The novelty lies in precisely stacking electrical and photonic integrated circuits with polymer waveguides and an integrated fan-out redistribution layer, enabling efficient optical communication directly within a compact chip package. This allows light to carry data between different chip layers, overcoming the speed and power limits of traditional electrical connections.
What it does not cover
- Does not cover optical interconnections that use glass fibers or other non-polymer materials for waveguides.
- Does not cover chip packages where the photonic integrated circuit is not placed directly on top of the electrical integrated circuit.
- Does not cover optical signal routing without an Integrated Fan-Out Redistribution Layer (InFO RDL) positioned on top of the polymer waveguides.
- Does not cover systems where light signals are not directed by an optical lens adjacent to the InFO RDL layer.
- Does not cover purely electrical connections between stacked chips without the use of optical waveguides.
- Does not cover waveguide structures that do not consist of a core layer surrounded by at least two cladding layers of different polymers.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
15/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
20/20
Granted within 5 years
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$35K – $112K
Midpoint $70K · 17.0 yr remaining · industry ×1.5
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
23 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Wu, C., Weng, C., Chen, Y., Kuan, J., & Lee, H. (2024). Stacking Chips with Light-Guiding Plastic Wires (U.S. Patent No. 12,181,722). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/12181722/structures-and-process-flow-for-integrated-photonic-electric-ic-package-by-using
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does Stacking Chips with Light-Guiding Plastic Wires cover?
TSMC's patent describes a method for building advanced chip packages that combine electrical and light-based circuits using polymer waveguides and an integrated fan-out redistribution layer for faster communication.
Who owns patent US 12181722?
Taiwan Semiconductor Manufacturing Co TSMC owns this patent, granted in 2024.
When does this patent expire?
This patent is expected to expire on August 9, 2043, when the invention enters the public domain.
What problem does this patent solve?
As computer chips become more powerful, the electrical wires connecting different parts of the chip struggle to keep up with the speed and amount of data. This patent offers a way to use light, which is much faster, to transmit data within a chip package. By integrating optical and electrical components closely, it helps overcome these bottlenecks, which is crucial for high-performance computing, artificial intelligence accelerators, and data centers.
What does this patent NOT cover?
Does not cover optical interconnections that use glass fibers or other non-polymer materials for waveguides.
Same assignee
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