How to Stack Computer Chips on a Wafer for Smaller Devices
This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package.
Original patent title: “Wafer level stack structure for system-in-package and method thereof”
This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package. Granted to Samsung Electronics Co in 2010 with 14 claims and 3 forward citations, and it is expected to expire in 2027.
Coverage
What does this patent actually cover?
This patent details a method for creating a stacked chip structure at the wafer level. It involves forming a first wafer with multiple 'first device chips,' each having an active 'first device region' and 'input/output (I/O) pads' within that region (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). Separately, a second wafer is formed with 'second device chips,' each having a 'second device region,' a 'second peripheral region' around it, and 'I/O pads' in its device region (Claim 1). A key aspect is that while the overall size of the first and second device chips is approximately equal, their active device regions are different sizes (Claim 1). For example, a memory chip (first device) could be stacked directly onto a logic chip (second device) while both are still part of their respective wafers. The two wafers are then stacked and connected, often using tiny conductive 'vias' and 'connection bumps' (ClaimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more → 7, 11) that might be rerouted on the second chip (Claim 10). After stacking, the combined wafers can be cut into individual chip stacks (Claim 12).
The gap
What does this patent NOT cover?
- Does not cover stacking individual chips after they have been cut from their wafers, as it specifically describes stacking entire wafers.
- Does not cover stacking chips where the overall dimensions of the first and second chips are significantly different, as they must be 'approximately equal in size' (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover stacking chips where the active functional areas ('device regions') are the same size, as they must have 'a different size' (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover designs where the input/output pads are located entirely outside the active 'device region' of the chip, as they are specified to be 'in the first device region' and 'in the second device region' (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover methods that do not involve a 'second peripheral region surrounding the second device region' (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The noveltynoveltyThe requirement that an invention be different from anything publicly known before its priority date.Read more → lies in the specific configuration for wafer-level stacking: it allows chips of roughly the same overall dimensions but with different active functional areas to be stacked and connected efficiently. This is managed by using a 'peripheral region' on one chip to accommodate the size difference in the active areas while maintaining overall chip alignment for wafer-level processing.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Memory-on-logic chip stacks in smartphones
Multi-chip modules for compact electronics
System-in-Package (SiP) solutions in wearables
3D stacked integrated circuits in high-performance computing
Image sensors with stacked processing logic
Why it matters
The bigger picture
This patent contributes to the field of advanced semiconductor packaging, specifically for creating System-in-Package (SiP) solutions. By stacking chips at the wafer level, manufacturers can create much smaller, faster, and more power-efficient electronic components. This approach reduces manufacturing costs and improves performance compared to stacking individual chips, which is vital for compact devices like smartphones and wearables.
Filed
March 28, 2007
Granted
November 2, 2010
Market context
Who's building on this
Companies in this space
Samsung Electronics Co Ltd, the original assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, remains a global leader in semiconductor manufacturing and continues to develop advanced packaging technologies. Other major semiconductor companies like TSMC, Intel, and Micron also invest heavily in wafer-level packaging and 3D stacking to create more compact and powerful integrated circuits for various applications.
Market impact
The development of wafer-level stacking methods has significantly impacted the semiconductor market by enabling greater integration and miniaturization. This technology is crucial for the continued shrinking of electronic devices, particularly in mobile and IoT sectors, by allowing multiple functions to be packed into a single, small package. It has driven innovation in packaging and assembly processes, leading to more complex and capable System-in-Package products.
Claim 1 — Plain English
What this patent covers
This patent details a method for creating a stacked chip structure at the wafer level. It involves forming a first wafer with multiple 'first device chips,' each having an active 'first device region' and 'input/output (I/O) pads' within that region (Claim 1). Separately, a second wafer is formed with 'second device chips,' each having a 'second device region,' a 'second peripheral region' around it, and 'I/O pads' in its device region (Claim 1). A key aspect is that while the overall size of the first and second device chips is approximately equal, their active device regions are different sizes (Claim 1). For example, a memory chip (first device) could be stacked directly onto a logic chip (second device) while both are still part of their respective wafers. The two wafers are then stacked and connected, often using tiny conductive 'vias' and 'connection bumps' (Claims 7, 11) that might be rerouted on the second chip (Claim 10). After stacking, the combined wafers can be cut into individual chip stacks (Claim 12).
The clever bit
The novelty lies in the specific configuration for wafer-level stacking: it allows chips of roughly the same overall dimensions but with different active functional areas to be stacked and connected efficiently. This is managed by using a 'peripheral region' on one chip to accommodate the size difference in the active areas while maintaining overall chip alignment for wafer-level processing.
What it does not cover
- Does not cover stacking individual chips after they have been cut from their wafers, as it specifically describes stacking entire wafers.
- Does not cover stacking chips where the overall dimensions of the first and second chips are significantly different, as they must be 'approximately equal in size' (Claim 1).
- Does not cover stacking chips where the active functional areas ('device regions') are the same size, as they must have 'a different size' (Claim 1).
- Does not cover designs where the input/output pads are located entirely outside the active 'device region' of the chip, as they are specified to be 'in the first device region' and 'in the second device region' (Claim 1).
- Does not cover methods that do not involve a 'second peripheral region surrounding the second device region' (Claim 1).
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Moderate
Citation count
12/40
Early citations
Claim breadth
9/20
Moderate scope
Recency
5/20
Granted 10–20 years ago
Assignee scale
20/20
Major company or institution
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$6K – $20K
Midpoint $13K · expired or expiring · industry ×1.4
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Patent Claims
0 independent claims · 1 dependent
Claims are the legal boundaries of the patent. An independent claim stands alone. A dependent claim adds limitations to its parent, narrowing — but not broadening — the scope.
The original legal language
Original claims
14 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Lee, K., Oh, S., Kim, G., & Song, Y. (2010). How to Stack Computer Chips on a Wafer for Smaller Devices (U.S. Patent No. 7,824,959). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/7824959/wafer-level-stack-structure-for-system-in-package-and-method-thereof
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How to Stack Computer Chips on a Wafer for Smaller Devices cover?
This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package.
Who owns patent US 7824959?
Samsung Electronics Co owns this patent, granted in 2010.
When does this patent expire?
This patent is expected to expire on March 28, 2027, when the invention enters the public domain.
What is patent US 7824959 cited by?
This patent has been cited by 3 later patents that build on its ideas.
What problem does this patent solve?
This patent contributes to the field of advanced semiconductor packaging, specifically for creating System-in-Package (SiP) solutions. By stacking chips at the wafer level, manufacturers can create much smaller, faster, and more power-efficient electronic components. This approach reduces manufacturing costs and improves performance compared to stacking individual chips, which is vital for compact devices like smartphones and wearables.
What does this patent NOT cover?
Does not cover stacking individual chips after they have been cut from their wafers, as it specifically describes stacking entire wafers.
Same assignee
More from Samsung Electronics Co
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