How to Stack Computer Chips on a Wafer for Smaller Devices

This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package.

What it covers

This patent details a method for creating a stacked chip structure at the wafer level. It involves forming a first wafer with multiple 'first device chips,' each having an active 'first device region' and 'input/output (I/O) pads' within that region (Claim 1). Separately, a second wafer is formed with 'second device chips,' each having a 'second device region,' a 'second peripheral region' around it, and 'I/O pads' in its device region (Claim 1). A key aspect is that while the overall size of the first and second device chips is approximately equal, their active device regions are different sizes (Claim 1). For example, a memory chip (first device) could be stacked directly onto a logic chip (second device) while both are still part of their respective wafers. The two wafers are then stacked and connected, often using tiny conductive 'vias' and 'connection bumps' (Claims 7, 11) that might be rerouted on the second chip (Claim 10). After stacking, the combined wafers can be cut into individual chip stacks (Claim 12).

What it doesn't cover

• —Does not cover stacking individual chips after they have been cut from their wafers, as it specifically describes stacking entire wafers.
• —Does not cover stacking chips where the overall dimensions of the first and second chips are significantly different, as they must be 'approximately equal in size' (Claim 1).
• —Does not cover stacking chips where the active functional areas ('device regions') are the same size, as they must have 'a different size' (Claim 1).
• —Does not cover designs where the input/output pads are located entirely outside the active 'device region' of the chip, as they are specified to be 'in the first device region' and 'in the second device region' (Claim 1).
• —Does not cover methods that do not involve a 'second peripheral region surrounding the second device region' (Claim 1).

The clever bit

The novelty lies in the specific configuration for wafer-level stacking: it allows chips of roughly the same overall dimensions but with different active functional areas to be stacked and connected efficiently. This is managed by using a 'peripheral region' on one chip to accommodate the size difference in the active areas while maintaining overall chip alignment for wafer-level processing.

Why it matters

This patent contributes to the field of advanced semiconductor packaging, specifically for creating System-in-Package (SiP) solutions. By stacking chips at the wafer level, manufacturers can create much smaller, faster, and more power-efficient electronic components. This approach reduces manufacturing costs and improves performance compared to stacking individual chips, which is vital for compact devices like smartphones and wearables.

Real-world examples

• 1.Memory-on-logic chip stacks in smartphones
• 2.Multi-chip modules for compact electronics
• 3.System-in-Package (SiP) solutions in wearables
• 4.3D stacked integrated circuits in high-performance computing
• 5.Image sensors with stacked processing logic