How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate
This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip.
Patent Number
US 10181457
Status
Active
Filing Date
October 24, 2016
Grant Date
January 15, 2019
Expiration
October 24, 2036
Claims
7
Assignee
Invensas
Inventors
Rajesh Katkar, Ashok S. Prabhu
Citations
13 forward · 952 backward
What it covers
Claim 1 describes a 'package-on-package device' that uses a 'metal substrate' with distinct 'outer conductive pads' and 'inner conductive pads'. A 'microelectronic device' connects to the 'inner conductive pads' via 'first interconnects', which can be 'posts' (Claim 4). 'Wire bond wires' attach to the 'outer conductive pads'. A 'redistribution layer' on the lower surface connects these pads. The key feature is that the 'outer conductive pads are located outside of a perimeter of the microelectronic device for the fan-out from the inner conductive pads located below the microelectronic device' (Claim 1). This allows connections to spread out beyond the chip's footprint. For example, a processor chip could be connected to memory chips stacked above it, with all connections efficiently routed to a larger circuit board below.
What it doesn't cover
- —Does not cover chip packages that do not use a metal substrate as the base (Claim 1).
- —Does not cover single-chip packages; it specifically claims a 'package-on-package device' (Claim 1).
- —Does not cover packaging where electrical connections do not 'fan-out' beyond the microelectronic device's perimeter (Claim 1).
- —Does not cover packages that connect chips without using both 'wire bond wires' and 'first interconnects' (posts) as described (Claim 1, 4).
- —Does not cover packages without a 'redistribution layer' connecting the pads on the lower surface (Claim 1).
The clever bit
The novelty lies in combining a metal substrate with electrically isolated inner and outer conductive pads, specifically designed for a 'package-on-package' configuration. This setup allows for efficient 'fan-out' of connections from both wire bonds and stacked chips, maximizing connectivity in a minimal footprint.
Why it matters
This technology is crucial for making smaller, more powerful electronic devices. By enabling the stacking of multiple chips (like a processor and memory) in a 'package-on-package' arrangement, it saves valuable space inside devices. The 'fan-out' capability allows for more electrical connections in a compact area, which is essential for high-performance chips in modern smartphones, wearables, and other miniaturized electronics.
Real-world examples
- 1.Smartphones
- 2.Wearable electronics
- 3.Internet of Things (IoT) devices
- 4.High-density memory modules
- 5.Automotive electronics control units
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