Making AI Chips Faster with Multiple Readers for Stored Data
This patent describes a specialized computer chip design that uses multiple reading components for each stored piece of information, allowing artificial intelligence calculations to happen much faster and more efficiently.
Original patent title: “Resistive processing unit with multiple weight readers”
This patent describes a specialized computer chip design that uses multiple reading components for each stored piece of information, allowing artificial intelligence calculations to happen much faster and more efficiently. Granted to International Business Machines in 2021 with 23 claims, and it is expected to expire in 2038.
Coverage
What does this patent actually cover?
This patent describes a "crossbar array" of tiny processing units, called "resistive processing unit (RPU) devices," each located at a "crosspoint." Each RPU device holds a "single weight storage element" that stores a value, but critically, it has "multiple weight reader elements" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). A first reader connects to a "first row wire" to calculate a "first matrix product value" using an incoming value and the stored value. Simultaneously, a second reader connects to a "second row wire" to calculate a "second matrix product value" using a different incoming value and the *same* stored value (Claim 1). This design allows the RPU devices to compute these matrix product values "concurrently" (Claim 6), meaning at the same time, which speeds up complex calculations. For example, in an AI system recognizing an object, this chip could process multiple features of an image against its learned knowledge simultaneously.
The gap
What does this patent NOT cover?
- Does not cover RPU devices where each stored value is read by only a single reader element.
- Does not cover RPU devices where each crosspoint has multiple weight storage elements instead of a single one.
- Does not cover processing units that are not 'resistive' in nature, focusing specifically on a resistive architecture.
- Does not cover general-purpose computing or mathematical operations other than matrix product calculations.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The truly clever part is the design choice to have multiple independent 'reader' components for a *single* piece of stored data within each processing unit. This allows the system to perform several calculations using the same stored value at the exact same time, avoiding the need to duplicate data or wait for sequential access.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Specialized AI accelerator chips
Neuromorphic computing hardware
Hardware for deep learning inference
High-performance computing for AI training
Why it matters
The bigger picture
Artificial intelligence and machine learning rely heavily on complex mathematical operations, especially matrix multiplication, which can be very time-consuming. This patent aims to make these core calculations much faster and more energy-efficient by allowing multiple parts of a calculation to happen at the same time within a single processing unit. This kind of innovation is crucial for developing more powerful AI models and deploying them in real-world applications, from self-driving cars to advanced medical diagnostics.
Filed
April 20, 2018
Granted
August 10, 2021
Market context
Who's building on this
Companies in this space
IBM, the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, is a leader in researching and developing advanced computing architectures, including those for AI and neuromorphic computing. Companies like Intel with its Loihi chip, Google with its Tensor Processing Units (TPUs), and NVIDIA with its specialized GPU cores are also actively developing hardware that accelerates matrix operations for AI.
Market impact
This patent contributes to the ongoing effort to design more efficient hardware for artificial intelligence. By proposing a method to speed up fundamental matrix multiplication operations, it aims to enable the development of faster, more powerful, and less energy-intensive AI systems. Such advancements are critical for the continued growth of AI across various industries, potentially leading to more sophisticated AI models and broader deployment in edge devices and data centers.
Claim 1 — Plain English
What this patent covers
This patent describes a "crossbar array" of tiny processing units, called "resistive processing unit (RPU) devices," each located at a "crosspoint." Each RPU device holds a "single weight storage element" that stores a value, but critically, it has "multiple weight reader elements" (Claim 1). A first reader connects to a "first row wire" to calculate a "first matrix product value" using an incoming value and the stored value. Simultaneously, a second reader connects to a "second row wire" to calculate a "second matrix product value" using a different incoming value and the *same* stored value (Claim 1). This design allows the RPU devices to compute these matrix product values "concurrently" (Claim 6), meaning at the same time, which speeds up complex calculations. For example, in an AI system recognizing an object, this chip could process multiple features of an image against its learned knowledge simultaneously.
The clever bit
The truly clever part is the design choice to have multiple independent 'reader' components for a *single* piece of stored data within each processing unit. This allows the system to perform several calculations using the same stored value at the exact same time, avoiding the need to duplicate data or wait for sequential access.
What it does not cover
- Does not cover RPU devices where each stored value is read by only a single reader element.
- Does not cover RPU devices where each crosspoint has multiple weight storage elements instead of a single one.
- Does not cover processing units that are not 'resistive' in nature, focusing specifically on a resistive architecture.
- Does not cover general-purpose computing or mathematical operations other than matrix product calculations.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
15/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
10/20
Granted 5–10 years ago
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$26K – $83K
Midpoint $52K · 11.5 yr remaining · industry ×1.6
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
23 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Haensch, W., Kim, S., & Gokmen, T. (2021). Making AI Chips Faster with Multiple Readers for Stored Data (U.S. Patent No. 11,087,204). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/11087204/resistive-processing-unit-with-multiple-weight-readers
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does Making AI Chips Faster with Multiple Readers for Stored Data cover?
This patent describes a specialized computer chip design that uses multiple reading components for each stored piece of information, allowing artificial intelligence calculations to happen much faster and more efficiently.
Who owns patent US 11087204?
International Business Machines owns this patent, granted in 2021.
When does this patent expire?
This patent is expected to expire on April 20, 2038, when the invention enters the public domain.
What problem does this patent solve?
Artificial intelligence and machine learning rely heavily on complex mathematical operations, especially matrix multiplication, which can be very time-consuming. This patent aims to make these core calculations much faster and more energy-efficient by allowing multiple parts of a calculation to happen at the same time within a single processing unit. This kind of innovation is crucial for developing more powerful AI models and deploying them in real-world applications, from self-driving cars to advanced medical diagnostics.
What does this patent NOT cover?
Does not cover RPU devices where each stored value is read by only a single reader element.
Same assignee
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