How to Fix Faulty Memory Cells in AI Chips
This patent describes a system that tests individual memory cells in AI chips for uneven behavior and then permanently disables the faulty ones before the chip starts learning, making AI training more efficient.
Original patent title: “Killing asymmetric resistive processing units for neural network training”
This patent describes a system that tests individual memory cells in AI chips for uneven behavior and then permanently disables the faulty ones before the chip starts learning, making AI training more efficient. Granted to International Business Machines in 2021 with 23 claims and 3 forward citations, and it is expected to expire in 2037.
Coverage
What does this patent actually cover?
The patent describes a system for improving neural network training on specialized hardware called Resistive Processing Unit (RPU) arrays. An RPU array has many tiny memory cells (RPUs) arranged in a grid, where each RPU's electrical state (its "conduction state") stores a "weight" for the AI. Before training begins, a controller measures each RPU's "asymmetry value" by sending a positive electrical pulse and a negative electrical pulse and comparing how much the RPU's conduction state changes for each (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). If an RPU's asymmetry is too high, meaning it behaves differently depending on the electrical direction, the system "burns" it by applying a high voltage to permanently disable it (Claim 2, Claim 6). This ensures only reliable RPUs are used for training.
The gap
What does this patent NOT cover?
- Does not cover systems that train neural networks on traditional silicon chips like CPUs or GPUs, as it specifically targets RPU arrays.
- Does not cover methods of improving RPU array performance that don't involve measuring and disabling asymmetric RPUs.
- Does not cover RPU arrays where faulty units are simply ignored or remapped instead of being physically "burned" by a high voltage.
- Does not cover identifying faulty RPUs *during* or *after* the neural network training process.
- Does not cover RPUs that store information without also locally performing data processing operations (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 9).
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The noveltynoveltyThe requirement that an invention be different from anything publicly known before its priority date.Read more → lies in proactively identifying and permanently disabling individual, unevenly behaving memory cells (RPUs) *before* the main AI training process even starts. This prevents faulty components from corrupting the learning process or requiring complex software workarounds later.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
IBM's AI hardware accelerators
Neuromorphic computing chips
In-memory computing architectures
Specialized AI training hardware
Why it matters
The bigger picture
Training large neural networks is computationally intensive and energy-hungry. This patent addresses a fundamental challenge in building specialized AI hardware: the inherent imperfections of analog memory components like RPUs. By identifying and disabling faulty RPUs early, it aims to make these AI accelerators more reliable and efficient, potentially speeding up AI development and reducing power consumption for complex models.
Filed
May 31, 2017
Granted
March 23, 2021
Market context
Who's building on this
Companies in this space
IBM, the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, is a major player in AI hardware research, including neuromorphic computing and analog AI accelerators. Other companies like Intel (with Loihi), SynSense, and various startups are also developing specialized hardware for AI inference and training that could benefit from similar reliability improvements in their memory arrays.
Market impact
This technology aims to improve the yield and reliability of specialized AI hardware, particularly those using analog memory components for in-memory computing. By making these chips more robust, it could accelerate the adoption of energy-efficient AI accelerators for training complex models, potentially reducing the cost and time required for AI development across various industries.
Claim 1 — Plain English
What this patent covers
The patent describes a system for improving neural network training on specialized hardware called Resistive Processing Unit (RPU) arrays. An RPU array has many tiny memory cells (RPUs) arranged in a grid, where each RPU's electrical state (its "conduction state") stores a "weight" for the AI. Before training begins, a controller measures each RPU's "asymmetry value" by sending a positive electrical pulse and a negative electrical pulse and comparing how much the RPU's conduction state changes for each (Claim 1). If an RPU's asymmetry is too high, meaning it behaves differently depending on the electrical direction, the system "burns" it by applying a high voltage to permanently disable it (Claim 2, Claim 6). This ensures only reliable RPUs are used for training.
The clever bit
The novelty lies in proactively identifying and permanently disabling individual, unevenly behaving memory cells (RPUs) *before* the main AI training process even starts. This prevents faulty components from corrupting the learning process or requiring complex software workarounds later.
What it does not cover
- Does not cover systems that train neural networks on traditional silicon chips like CPUs or GPUs, as it specifically targets RPU arrays.
- Does not cover methods of improving RPU array performance that don't involve measuring and disabling asymmetric RPUs.
- Does not cover RPU arrays where faulty units are simply ignored or remapped instead of being physically "burned" by a high voltage.
- Does not cover identifying faulty RPUs *during* or *after* the neural network training process.
- Does not cover RPUs that store information without also locally performing data processing operations (Claim 9).
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
12/40
Early citations
Claim breadth
15/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
10/20
Granted 5–10 years ago
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$78K – $250K
Midpoint $156K · 10.9 yr remaining · industry ×1.6
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
The original legal language
Original claims
23 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Gokmen, T. (2021). How to Fix Faulty Memory Cells in AI Chips (U.S. Patent No. 10,956,815). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/10956815/killing-asymmetric-resistive-processing-units-for-neural-network-training
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
Embed
Add this patent to your site
Drop this plain-English patent card into any blog post or article — free, no signup. It always links back to the full breakdown here.
<div data-patentlens-widget data-patent-number="US10956815"></div> <script src="https://patentbrief.org/embed.js" async></script>
Stay in the loop
Get a weekly digest of new patents.
One email per week. No spam. Unsubscribe anytime.
Keep exploring
Related patents you should know
US 4683195 · 1987
How to Make Billions of Copies of a DNA Segment
This patent describes the Polymerase Chain Reaction (PCR), a method to rapidly create many copies of a specific piece of DNA or RNA, enabling its detection and analysis.
Cetus Corp
US 8697359 · 2014
How to Edit Genes in Human Cells Using an Engineered CRISPR System
This patent describes an engineered CRISPR-Cas9 system for precisely cutting DNA in eukaryotic cells to change how genes work, opening the door for gene editing in complex organisms.
Massachusetts Institute of Technology
US 7657849 · 2010
How the iPhone's Slide-to-Unlock Gesture Works
Apple's 2010 patent describes unlocking a device by dragging a specific graphical image across the touchscreen along a predefined path, a gesture that became iconic with the original iPhone.
Apple Inc
US 4733665 · 1988
How Doctors Implant a Permanent Stent Using a Balloon
This patent describes the method for placing a permanent, expandable wire mesh tube inside a blood vessel or other body tube using a balloon-tipped catheter to widen it and keep it open.
Expandable Grafts Partnership
US 4965188 · 1990
How to Make Many Copies of a DNA Piece with Heat
This patent describes the Polymerase Chain Reaction (PCR) method, a technique to make millions of copies of a specific DNA segment using a heat-resistant enzyme and repeated temperature changes.
Cetus Corp
US 4235871 · 1980
How to Encapsulate Active Materials in Lipid Bubbles Efficiently
This patent describes a method for trapping biologically active substances inside tiny, multi-layered fat bubbles called liposomes, using a specific water-in-oil emulsion and gel-forming process to improve how much material gets captured.
Individual
Semantically similar
You might also find these interesting
US 10248907 · 2019 · International Business Machines
How a Single Electronic Component Can Learn and Process AI Data
US 11741188 · 2023 · Western Digital Technologies
How a Chip Uses Memory to Speed Up AI Calculations
US 10410117 · 2019 · BrainChip Inc
How to Save and Reuse Skills Learned by Artificial Intelligence Hardware
US 10832138 · 2020 · Samsung Electronics Co Ltd
How to Automatically Expand Neural Networks by Adding New Nodes
More to explore
More in Semiconductors & Chips
US 5563422 · 1996 · Nichia Chemical Industries Ltd
How Nichia Created the First Practical Blue LED Electrodes
US 10373050 · 2019 · Qualcomm Inc
How to Make AI Run Faster on Smaller Computer Chips
US 2981877 · 1961 · Fairchild Semiconductor Corp
How Robert Noyce Invented the Modern Integrated Circuit
US 2569347 · 1951 · Bell Telephone Laboratories Inc
The Invention of the Junction Transistor
New to patents?
Common Questions
Frequently Asked Questions
What does How to Fix Faulty Memory Cells in AI Chips cover?
This patent describes a system that tests individual memory cells in AI chips for uneven behavior and then permanently disables the faulty ones before the chip starts learning, making AI training more efficient.
Who owns patent US 10956815?
International Business Machines owns this patent, granted in 2021.
When does this patent expire?
This patent is expected to expire on May 31, 2037, when the invention enters the public domain.
What is patent US 10956815 cited by?
This patent has been cited by 3 later patents that build on its ideas.
What problem does this patent solve?
Training large neural networks is computationally intensive and energy-hungry. This patent addresses a fundamental challenge in building specialized AI hardware: the inherent imperfections of analog memory components like RPUs. By identifying and disabling faulty RPUs early, it aims to make these AI accelerators more reliable and efficient, potentially speeding up AI development and reducing power consumption for complex models.
What does this patent NOT cover?
Does not cover systems that train neural networks on traditional silicon chips like CPUs or GPUs, as it specifically targets RPU arrays.
Same assignee
More from International Business Machines
Patent monitoring