How a Chip Uses Memory to Speed Up AI Calculations
This patent describes a specialized computer chip that uses non-volatile memory and analog signals to quickly perform calculations for artificial intelligence, especially for neural networks that need to remember past information.
Original patent title: “Hardware accelerated discretized neural network”
This patent describes a specialized computer chip that uses non-volatile memory and analog signals to quickly perform calculations for artificial intelligence, especially for neural networks that need to remember past information. Granted to Western Digital Technologies in 2023 with 23 claims, and it is expected to expire in 2041.
Coverage
What does this patent actually cover?
This patent describes a device and method for speeding up neural network calculations using specialized hardware. It starts by converting digital input signals into analog signals using a Digital-to-Analog Converter (DAC). These analog signals then go into non-volatile memory (NVM) weight arrays, which perform complex math called vector matrix multiplication (VMM). A key part is that each "synaptic weight element" (like a connection strength in a brain model) is represented by multiple parallel NVM cells, such as at least three parallel NVM cells (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 4, 13), which helps with accuracy. After the VMM, Analog-to-Digital Converters (ADCs) turn the analog results back into digital values. A "neural circuit" then processes these digital values, applying activation functions to calculate a "new memory cell state" (Claim 1, 10), which can be fed back for the next calculation cycle, useful for AI that processes sequences like language.
The gap
What does this patent NOT cover?
- Does not cover neural network computations performed entirely in the digital domain without analog conversion.
- Does not cover systems where synaptic weight elements are represented by a single NVM cell, as it specifies "multiple parallel NVM cells" (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1, 10).
- Does not cover VMM computations performed using volatile memory (like DRAM or SRAM) instead of non-volatile memory (NVM) weight arrays.
- Does not cover systems that do not convert digital input signals to analog for VMM computation.
- Does not cover systems that do not convert analog VMM results back to digital values using ADCs.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The clever part is using multiple parallel non-volatile memory (NVM) cells to represent a single "synaptic weight element" and performing vector matrix multiplication (VMM) in the analog domain. This allows for higher precision and robustness in analog computing, which is typically noisy, and enables efficient in-memory computation, reducing data movement bottlenecks.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
AI accelerators for edge devices
Specialized chips for neural network inference
Smartphones with dedicated AI processing units
IoT devices performing local AI tasks
Data center AI inference engines
Why it matters
The bigger picture
This technology matters because it addresses a major challenge in AI: making neural networks run faster and more efficiently, especially on devices with limited power like smartphones or IoT sensors. By performing calculations directly within memory using analog signals, it can potentially reduce the energy and time needed to move data between a processor and memory. This approach is crucial for deploying advanced AI models, such as those used in natural language processing or voice assistants, directly on edge devices without relying on constant cloud connectivity.
Filed
July 8, 2021
Granted
August 29, 2023
Market context
Who's building on this
Companies in this space
Western Digital Technologies Inc., the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, is a major player in memory and storage solutions, and this patent aligns with their interest in developing advanced memory architectures for computing. Other companies like Samsung, SK Hynix, Micron, and various AI chip startups are also actively researching and developing in-memory computing and analog AI accelerators, aiming to integrate AI capabilities directly into memory or specialized processing units.
Market impact
This patent contributes to the ongoing shift towards more energy-efficient and faster AI processing, particularly for edge devices. It supports the development of specialized hardware that can accelerate neural network inference, potentially reducing the reliance on powerful cloud servers for real-time AI tasks. This could enable new product categories in IoT, autonomous systems, and advanced consumer electronics by making sophisticated AI more accessible and ubiquitous.
Claim 1 — Plain English
What this patent covers
This patent describes a device and method for speeding up neural network calculations using specialized hardware. It starts by converting digital input signals into analog signals using a Digital-to-Analog Converter (DAC). These analog signals then go into non-volatile memory (NVM) weight arrays, which perform complex math called vector matrix multiplication (VMM). A key part is that each "synaptic weight element" (like a connection strength in a brain model) is represented by multiple parallel NVM cells, such as at least three parallel NVM cells (Claim 4, 13), which helps with accuracy. After the VMM, Analog-to-Digital Converters (ADCs) turn the analog results back into digital values. A "neural circuit" then processes these digital values, applying activation functions to calculate a "new memory cell state" (Claim 1, 10), which can be fed back for the next calculation cycle, useful for AI that processes sequences like language.
The clever bit
The clever part is using multiple parallel non-volatile memory (NVM) cells to represent a single "synaptic weight element" and performing vector matrix multiplication (VMM) in the analog domain. This allows for higher precision and robustness in analog computing, which is typically noisy, and enables efficient in-memory computation, reducing data movement bottlenecks.
What it does not cover
- Does not cover neural network computations performed entirely in the digital domain without analog conversion.
- Does not cover systems where synaptic weight elements are represented by a single NVM cell, as it specifies "multiple parallel NVM cells" (Claim 1, 10).
- Does not cover VMM computations performed using volatile memory (like DRAM or SRAM) instead of non-volatile memory (NVM) weight arrays.
- Does not cover systems that do not convert digital input signals to analog for VMM computation.
- Does not cover systems that do not convert analog VMM results back to digital values using ADCs.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
15/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
20/20
Granted within 5 years
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$37K – $120K
Midpoint $75K · 15.0 yr remaining · industry ×1.6
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
The original legal language
Original claims
23 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Chiu, P., Choi, W. H., LUEKER-BODEN, M., Qin, M., & Ma, W. (2023). How a Chip Uses Memory to Speed Up AI Calculations (U.S. Patent No. 11,741,188). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/11741188/hardware-accelerated-discretized-neural-network
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How a Chip Uses Memory to Speed Up AI Calculations cover?
This patent describes a specialized computer chip that uses non-volatile memory and analog signals to quickly perform calculations for artificial intelligence, especially for neural networks that need to remember past information.
Who owns patent US 11741188?
Western Digital Technologies owns this patent, granted in 2023.
When does this patent expire?
This patent is expected to expire on July 8, 2041, when the invention enters the public domain.
What problem does this patent solve?
This technology matters because it addresses a major challenge in AI: making neural networks run faster and more efficiently, especially on devices with limited power like smartphones or IoT sensors. By performing calculations directly within memory using analog signals, it can potentially reduce the energy and time needed to move data between a processor and memory. This approach is crucial for deploying advanced AI models, such as those used in natural language processing or voice assistants, directly on edge devices without relying on constant cloud connectivity.
What does this patent NOT cover?
Does not cover neural network computations performed entirely in the digital domain without analog conversion.
Patent monitoring