Training AI Chips Using Memristor Crossbars Directly On-Chip
This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently.
Original patent title: “On-chip training of memristor crossbar neuromorphic processing systems”
This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently. Owned by University of Dayton with 24 claims, and it is expected to expire in 2043.
Coverage
What does this patent actually cover?
This patent describes an analog neuromorphic circuit designed for on-chip training of artificial intelligence. It uses a grid of 'resistive memories' (like memristors) that can change how much they resist electrical current. When an 'input voltage signal' goes through these memories, it creates a 'first output voltage signal' (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1). A 'first comparator' then checks this output against a 'desired output signal' and figures out the difference, creating a 'first error signal' (Claim 1). This error signal then travels *backwards* through the *same* resistive memories, generating a 'second output voltage signal' (Claim 1). Finally, a 'resistance adjuster' tweaks the resistance of each memory based on both the error signal and the second output, aiming to make the first output closer to the desired one (Claim 1). For example, if the circuit is trying to recognize a handwritten 'A' but outputs something closer to a 'B', the error signal helps the memristors adjust their internal connections to correctly identify 'A' next time.
The gap
What does this patent NOT cover?
- Does not cover neuromorphic circuits that perform training off-chip, requiring data to be sent to a separate processor.
- Does not cover systems that use different sets of resistive memories or components for the forward pass and the error back-propagation steps (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 6).
- Does not cover digital neuromorphic circuits, as the claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more → specifically refer to an 'analog neuromorphic circuit' (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover training methods where the resistance adjustment is not based on both a 'first error signal' and a 'second output voltage signal' generated by the backward pass (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1).
- Does not cover circuits where the resistive memories are not arranged in a grid configuration with distinct vertical and horizontal neuron groupings for signal and error propagation (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 3, 5).
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The truly clever part is reusing the *same* set of resistive memories for both the forward pass (processing the input) and the backward pass (propagating the error signal to adjust the memories). This eliminates the need for duplicate hardware, making the on-chip training more compact and energy-efficient.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Neuromorphic processors for edge AI devices
Self-learning sensors
AI accelerators for autonomous vehicles
Smart home devices with adaptive learning capabilities
Robotics with real-time learning
Why it matters
The bigger picture
Traditional AI training often happens on powerful computers, then the trained model is put onto a smaller chip for use. This patent aims to allow the training itself to happen directly on the chip, which could make AI devices more efficient, faster, and able to learn new things in real-time without needing to connect to a cloud server. This is crucial for edge AI applications where power and latency are critical.
Filed
September 5, 2023
Market context
Who's building on this
Companies in this space
Many research institutions and companies like IBM, Intel, and startups such as Mythic and BrainChip are actively developing neuromorphic computing hardware. The University of Dayton, as the assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, is also continuing research in this area. This patent contributes to the broader effort to create more efficient and adaptable AI hardware, particularly for edge computing applications.
Market impact
This technology aims to shift the paradigm of AI deployment by enabling devices to learn and adapt locally, rather than relying on cloud-based training. If successfully commercialized, it could lead to a new generation of smart devices that are more autonomous, secure, and responsive. It could also reduce the energy consumption associated with AI, making it more sustainable for widespread use in various industries.
Claim 1 — Plain English
What this patent covers
This patent describes an analog neuromorphic circuit designed for on-chip training of artificial intelligence. It uses a grid of 'resistive memories' (like memristors) that can change how much they resist electrical current. When an 'input voltage signal' goes through these memories, it creates a 'first output voltage signal' (Claim 1). A 'first comparator' then checks this output against a 'desired output signal' and figures out the difference, creating a 'first error signal' (Claim 1). This error signal then travels *backwards* through the *same* resistive memories, generating a 'second output voltage signal' (Claim 1). Finally, a 'resistance adjuster' tweaks the resistance of each memory based on both the error signal and the second output, aiming to make the first output closer to the desired one (Claim 1). For example, if the circuit is trying to recognize a handwritten 'A' but outputs something closer to a 'B', the error signal helps the memristors adjust their internal connections to correctly identify 'A' next time.
The clever bit
The truly clever part is reusing the *same* set of resistive memories for both the forward pass (processing the input) and the backward pass (propagating the error signal to adjust the memories). This eliminates the need for duplicate hardware, making the on-chip training more compact and energy-efficient.
What it does not cover
- Does not cover neuromorphic circuits that perform training off-chip, requiring data to be sent to a separate processor.
- Does not cover systems that use different sets of resistive memories or components for the forward pass and the error back-propagation steps (Claim 6).
- Does not cover digital neuromorphic circuits, as the claims specifically refer to an 'analog neuromorphic circuit' (Claim 1).
- Does not cover training methods where the resistance adjustment is not based on both a 'first error signal' and a 'second output voltage signal' generated by the backward pass (Claim 1).
- Does not cover circuits where the resistive memories are not arranged in a grid configuration with distinct vertical and horizontal neuron groupings for signal and error propagation (Claim 3, 5).
Patent timeline
Application submitted to the patent office
Patent enters public domain
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
16/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
0/20
Older than 20 years
Assignee scale
20/20
Major company or institution
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$31K – $100K
Midpoint $62K · 16.9 yr remaining · industry ×1.6
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
24 claims as filed with the patent office.
Concepts involved
Cite this patent
Taha, T. M., Hasan, M. R., & Yakopcic, C. Training AI Chips Using Memristor Crossbars Directly On-Chip (U.S. Patent No. 20,230,409,893). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/20230409893/on-chip-training-of-memristor-crossbar-neuromorphic-processing-systems
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does Training AI Chips Using Memristor Crossbars Directly On-Chip cover?
This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently.
Who owns patent US 20230409893?
This patent is owned by University of Dayton.
When does this patent expire?
This patent is expected to expire on September 5, 2043, when the invention enters the public domain.
What problem does this patent solve?
Traditional AI training often happens on powerful computers, then the trained model is put onto a smaller chip for use. This patent aims to allow the training itself to happen directly on the chip, which could make AI devices more efficient, faster, and able to learn new things in real-time without needing to connect to a cloud server. This is crucial for edge AI applications where power and latency are critical.
What does this patent NOT cover?
Does not cover neuromorphic circuits that perform training off-chip, requiring data to be sent to a separate processor.
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