Training AI Chips Using Memristor Crossbars Directly On-Chip

This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently.

What it covers

This patent describes an analog neuromorphic circuit designed for on-chip training of artificial intelligence. It uses a grid of 'resistive memories' (like memristors) that can change how much they resist electrical current. When an 'input voltage signal' goes through these memories, it creates a 'first output voltage signal' (Claim 1). A 'first comparator' then checks this output against a 'desired output signal' and figures out the difference, creating a 'first error signal' (Claim 1). This error signal then travels *backwards* through the *same* resistive memories, generating a 'second output voltage signal' (Claim 1). Finally, a 'resistance adjuster' tweaks the resistance of each memory based on both the error signal and the second output, aiming to make the first output closer to the desired one (Claim 1). For example, if the circuit is trying to recognize a handwritten 'A' but outputs something closer to a 'B', the error signal helps the memristors adjust their internal connections to correctly identify 'A' next time.

What it doesn't cover

• —Does not cover neuromorphic circuits that perform training off-chip, requiring data to be sent to a separate processor.
• —Does not cover systems that use different sets of resistive memories or components for the forward pass and the error back-propagation steps (Claim 6).
• —Does not cover digital neuromorphic circuits, as the claims specifically refer to an 'analog neuromorphic circuit' (Claim 1).
• —Does not cover training methods where the resistance adjustment is not based on both a 'first error signal' and a 'second output voltage signal' generated by the backward pass (Claim 1).
• —Does not cover circuits where the resistive memories are not arranged in a grid configuration with distinct vertical and horizontal neuron groupings for signal and error propagation (Claim 3, 5).

The clever bit

The truly clever part is reusing the *same* set of resistive memories for both the forward pass (processing the input) and the backward pass (propagating the error signal to adjust the memories). This eliminates the need for duplicate hardware, making the on-chip training more compact and energy-efficient.

Why it matters

Traditional AI training often happens on powerful computers, then the trained model is put onto a smaller chip for use. This patent aims to allow the training itself to happen directly on the chip, which could make AI devices more efficient, faster, and able to learn new things in real-time without needing to connect to a cloud server. This is crucial for edge AI applications where power and latency are critical.

Real-world examples

• 1.Neuromorphic processors for edge AI devices
• 2.Self-learning sensors
• 3.AI accelerators for autonomous vehicles
• 4.Smart home devices with adaptive learning capabilities
• 5.Robotics with real-time learning