How to Combine FPGA and Non-Volatile Memory Chips in One Package
This patent describes a compact chip package that integrates multiple semiconductor chips, specifically an FPGA and a non-volatile memory chip, using precisely dimensioned metal and dielectric layers over a polymer layer for a logic drive.
Original patent title: “Non-volatile programmable logic device based on multi-chip package”
This patent describes a compact chip package that integrates multiple semiconductor chips, specifically an FPGA and a non-volatile memory chip, using precisely dimensioned metal and dielectric layers over a polymer layer for a logic drive. Granted in 2026.
Coverage
What does this patent actually cover?
This patent describes a chip package designed as a logic drive. It includes multiple semiconductor chips, with a polymer layer placed horizontally between them. Over these chips and the polymer layer are multiple metal layers, which connect to the chips and extend across their edges. One of these metal layers has a thickness and trace width between 0.5 and 5 micrometers. Similarly, multiple dielectric layers are placed between the metal layers and also extend across the chip edges, with one dielectric layer having a thickness between 0.5 and 5 micrometers. The package uses metal bumps on its top metal layer for external connections. Crucially, one of the semiconductor chips is an FPGA IC chip, and another is a non-volatile memory (NVMIC) chip, enabling a programmable logic device with integrated persistent storage.
The gap
What does this patent NOT cover?
- Does not cover chip packages that do not include a polymer layer placed horizontally between the semiconductor chips.
- Does not cover packages that combine different types of chips, such as a CPU and a GPU, as it specifically claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more → an FPGA and a NVMIC.
- Does not cover packages where the metal or dielectric layers have thicknesses or trace widths outside the specified range of 0.5 to 5 micrometers.
- Does not cover single-chip packages, as it explicitly requires multiple semiconductor chips.
- Does not cover packages where the metal and dielectric layers do not extend across the edges of the semiconductor chips.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The clever bit is the precise structural integration of different chip types, specifically an FPGA and NVMIC, within a single package. This is achieved through a polymer layer horizontally separating chips, and finely dimensioned metal and dielectric layers that extend across the chip edges, enabling compact, high-speed interconnections and efficient power delivery for a logic drive.
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
System-in-Package (SiP) modules for embedded systems
Specialized computing modules for AI acceleration
Compact control units in industrial automation
FPGA-based network processing units with integrated configuration memory
Why it matters
The bigger picture
Integrating Field-Programmable Gate Arrays (FPGAs) with non-volatile memory (NVM) in a single package is vital for modern electronics. FPGAs require configuration data, and NVM provides persistent storage for this data, allowing instant-on functionality and reducing boot times. This compact integration saves valuable board space, reduces power consumption, and improves performance by minimizing the distance between the FPGA and its configuration memory, which is critical for embedded systems and edge computing devices.
Filed
March 24, 2023
Granted
September 15, 2026
Market context
Who's building on this
Companies in this space
Major semiconductor companies like AMD (which acquired Xilinx, a leading FPGA maker) and Intel (with its Altera FPGAs) are continuously developing advanced packaging technologies to integrate FPGAs with memory and other components. Companies specializing in advanced packaging, such as Amkor Technology and ASE Group, are also key players in developing multi-chip packages that align with the principles described in this patent.
Market impact
This type of multi-chip packaging has significantly impacted markets requiring high-performance, compact, and power-efficient programmable logic. It enables smaller form factors for devices, which is crucial for embedded systems, IoT devices, and edge AI applications. By reducing the physical distance between FPGAs and their non-volatile configuration memory, it improves system speed and reduces latency, fostering innovation in areas like real-time data processing and custom hardware acceleration.
Claim 1 — Plain English
What this patent covers
This patent describes a chip package designed as a logic drive. It includes multiple semiconductor chips, with a polymer layer placed horizontally between them. Over these chips and the polymer layer are multiple metal layers, which connect to the chips and extend across their edges. One of these metal layers has a thickness and trace width between 0.5 and 5 micrometers. Similarly, multiple dielectric layers are placed between the metal layers and also extend across the chip edges, with one dielectric layer having a thickness between 0.5 and 5 micrometers. The package uses metal bumps on its top metal layer for external connections. Crucially, one of the semiconductor chips is an FPGA IC chip, and another is a non-volatile memory (NVMIC) chip, enabling a programmable logic device with integrated persistent storage.
The clever bit
The clever bit is the precise structural integration of different chip types, specifically an FPGA and NVMIC, within a single package. This is achieved through a polymer layer horizontally separating chips, and finely dimensioned metal and dielectric layers that extend across the chip edges, enabling compact, high-speed interconnections and efficient power delivery for a logic drive.
What it does not cover
- Does not cover chip packages that do not include a polymer layer placed horizontally between the semiconductor chips.
- Does not cover packages that combine different types of chips, such as a CPU and a GPU, as it specifically claims an FPGA and a NVMIC.
- Does not cover packages where the metal or dielectric layers have thicknesses or trace widths outside the specified range of 0.5 to 5 micrometers.
- Does not cover single-chip packages, as it explicitly requires multiple semiconductor chips.
- Does not cover packages where the metal and dielectric layers do not extend across the edges of the semiconductor chips.
Patent timeline
Application submitted to the patent office
Patent officially issued
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
0/20
Narrow claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
20/20
Granted within 5 years
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$18K – $58K
Midpoint $36K · 16.5 yr remaining · industry ×1.5
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
Concepts involved
Cite this patent
(2026). How to Combine FPGA and Non-Volatile Memory Chips in One Package (U.S. Patent No. 12,737,520). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/12737520/non-volatile-programmable-logic-device-based-on-multi-chip-package
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How to Combine FPGA and Non-Volatile Memory Chips in One Package cover?
This patent describes a compact chip package that integrates multiple semiconductor chips, specifically an FPGA and a non-volatile memory chip, using precisely dimensioned metal and dielectric layers over a polymer layer for a logic drive.
When does this patent expire?
This patent is expected to expire on September 15, 2046, when the invention enters the public domain.
What problem does this patent solve?
Integrating Field-Programmable Gate Arrays (FPGAs) with non-volatile memory (NVM) in a single package is vital for modern electronics. FPGAs require configuration data, and NVM provides persistent storage for this data, allowing instant-on functionality and reducing boot times. This compact integration saves valuable board space, reduces power consumption, and improves performance by minimizing the distance between the FPGA and its configuration memory, which is critical for embedded systems and edge computing devices.
What does this patent NOT cover?
Does not cover chip packages that do not include a polymer layer placed horizontally between the semiconductor chips.
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