How Xilinx Chips Quickly Check If Memory Is Completely Erased
A method for programmable chips to instantly verify that all memory cells are wiped clean using a simple, high-speed logic gate circuit.
Original patent title: “High-speed minimal logic self blank checking method for programmable logic device”
A method for programmable chips to instantly verify that all memory cells are wiped clean using a simple, high-speed logic gate circuit. Granted to Xilinx Inc in 1996 with 24 claims and 5 forward citations, and it is now in the public domain.
Coverage
What does this patent actually cover?
This patent describes a hardware circuit designed to verify if memory cells in a programmable logic device (PLD) are fully erased. It uses an n-input NOR gate formed by NMOS transistors connected to sense amplifiers. When a wordline is activated, the circuit checks all memory cells on that line simultaneously. If any single cell is not fully erased, its sense amplifier outputs a high signal, which turns on an NMOS transistor and pulls the common output node low, signaling that the device is not yet clean.
The gap
What does this patent NOT cover?
- Does not cover software-based verification methods that check memory cells one by one.
- Does not cover memory architectures that do not use sense amplifiers as input sources for the gate.
- Does not cover non-volatile memory technologies that do not utilize wordline-based addressing.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
Instead of reading each cell individually, the circuit uses the physical properties of a NOR gate to perform a parallel 'all-or-nothing' check, where a single un-erased cell immediately forces the output to a 'not erased' state.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Xilinx FPGA configuration memory
Programmable logic device (PLD) erasure cycles
High-density memory array testing
Why it matters
The bigger picture
Before this, checking if a large programmable chip was fully erased could be a slow, iterative process. By implementing this logic gate directly into the hardware, Xilinx made the erasure verification process nearly instantaneous, which is critical for manufacturing efficiency and device reliability in field-programmable gate arrays (FPGAs).
Filed
March 3, 1995
Granted
October 1, 1996
Market context
Who's building on this
Companies in this space
Xilinx, now part of AMD, remains a leader in FPGA technology. The fundamental principles of efficient memory testing and configuration verification are standard in modern high-density programmable logic devices produced by companies like Intel (formerly Altera) and Lattice Semiconductor.
Market impact
This patent helped standardize high-speed verification in the FPGA industry, allowing manufacturers to reduce testing time during production. It enabled the reliable scaling of programmable devices by ensuring that configuration memory could be cleared and verified rapidly without bottlenecking the manufacturing flow.
Claim 1 — Plain English
What this patent covers
This patent describes a hardware circuit designed to verify if memory cells in a programmable logic device (PLD) are fully erased. It uses an n-input NOR gate formed by NMOS transistors connected to sense amplifiers. When a wordline is activated, the circuit checks all memory cells on that line simultaneously. If any single cell is not fully erased, its sense amplifier outputs a high signal, which turns on an NMOS transistor and pulls the common output node low, signaling that the device is not yet clean.
The clever bit
Instead of reading each cell individually, the circuit uses the physical properties of a NOR gate to perform a parallel 'all-or-nothing' check, where a single un-erased cell immediately forces the output to a 'not erased' state.
What it does not cover
- Does not cover software-based verification methods that check memory cells one by one.
- Does not cover memory architectures that do not use sense amplifiers as input sources for the gate.
- Does not cover non-volatile memory technologies that do not utilize wordline-based addressing.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
This patent is in the public domain
See the Freedom to Build guide — what is free to use, what is not, and how to cite this patent.
PatentBrief Score
Impact Score
Early stage
Citation count
16/40
Early citations
Claim breadth
16/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
0/20
Older than 20 years
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$7K – $22K
Midpoint $14K · expired or expiring · industry ×1.4
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Patent Claims
0 independent claims · 1 dependent
Claims are the legal boundaries of the patent. An independent claim stands alone. A dependent claim adds limitations to its parent, narrowing — but not broadening — the scope.
The original legal language
Original claims
24 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Curd, D. R. (1996). How Xilinx Chips Quickly Check If Memory Is Completely Erased (U.S. Patent No. 5,561,631). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/5561631/high-speed-minimal-logic-self-blank-checking-method-for-programmable-logic-device
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
Embed
Add this patent to your site
Drop this plain-English patent card into any blog post or article — free, no signup. It always links back to the full breakdown here.
<div data-patentlens-widget data-patent-number="US5561631"></div> <script src="https://patentbrief.org/embed.js" async></script>
Stay in the loop
Get a weekly digest of new patents.
One email per week. No spam. Unsubscribe anytime.
Keep exploring
Related patents you should know
US 4683195 · 1987
How to Make Billions of Copies of a DNA Segment
This patent describes the Polymerase Chain Reaction (PCR), a method to rapidly create many copies of a specific piece of DNA or RNA, enabling its detection and analysis.
Cetus Corp
US 8697359 · 2014
How to Edit Genes in Human Cells Using an Engineered CRISPR System
This patent describes an engineered CRISPR-Cas9 system for precisely cutting DNA in eukaryotic cells to change how genes work, opening the door for gene editing in complex organisms.
Massachusetts Institute of Technology
US 7657849 · 2010
How the iPhone's Slide-to-Unlock Gesture Works
Apple's 2010 patent describes unlocking a device by dragging a specific graphical image across the touchscreen along a predefined path, a gesture that became iconic with the original iPhone.
Apple Inc
US 4733665 · 1988
How Doctors Implant a Permanent Stent Using a Balloon
This patent describes the method for placing a permanent, expandable wire mesh tube inside a blood vessel or other body tube using a balloon-tipped catheter to widen it and keep it open.
Expandable Grafts Partnership
US 4965188 · 1990
How to Make Many Copies of a DNA Piece with Heat
This patent describes the Polymerase Chain Reaction (PCR) method, a technique to make millions of copies of a specific DNA segment using a heat-resistant enzyme and repeated temperature changes.
Cetus Corp
US 4235871 · 1980
How to Encapsulate Active Materials in Lipid Bubbles Efficiently
This patent describes a method for trapping biologically active substances inside tiny, multi-layered fat bubbles called liposomes, using a specific water-in-oil emulsion and gel-forming process to improve how much material gets captured.
Individual
Semantically similar
You might also find these interesting
US 4531203 · 1985 · Tokyo Shibaura Electric Co Ltd
How Flash Memory Cells Use an Erase Gate to Clear Data
US 5903495 · 1999 · Toshiba Corp
How Multi-Level Cell Memory Stores More Data in Less Space
US 11741188 · 2023 · Western Digital Technologies
How a Chip Uses Memory to Speed Up AI Calculations
US 3387286 · 1968 · International Business Machines Corp
How Robert Dennard Invented the One-Transistor DRAM Memory Cell
More to explore
More in Semiconductors & Chips
US 5563422 · 1996 · Nichia Chemical Industries Ltd
How Nichia Created the First Practical Blue LED Electrodes
US 10373050 · 2019 · Qualcomm Inc
How to Make AI Run Faster on Smaller Computer Chips
US 2981877 · 1961 · Fairchild Semiconductor Corp
How Robert Noyce Invented the Modern Integrated Circuit
US 2569347 · 1951 · Bell Telephone Laboratories Inc
The Invention of the Junction Transistor
New to patents?
Common Questions
Frequently Asked Questions
What does How Xilinx Chips Quickly Check If Memory Is Completely Erased cover?
A method for programmable chips to instantly verify that all memory cells are wiped clean using a simple, high-speed logic gate circuit.
Who owns patent US 5561631?
Xilinx Inc owns this patent, granted in 1996.
When does this patent expire?
This patent has expired and is now in the public domain — anyone can use the invention freely.
What is patent US 5561631 cited by?
This patent has been cited by 5 later patents that build on its ideas.
What problem does this patent solve?
Before this, checking if a large programmable chip was fully erased could be a slow, iterative process. By implementing this logic gate directly into the hardware, Xilinx made the erasure verification process nearly instantaneous, which is critical for manufacturing efficiency and device reliability in field-programmable gate arrays (FPGAs).
What does this patent NOT cover?
Does not cover software-based verification methods that check memory cells one by one.
Patent monitoring