Making Memory Chips Faster by Splitting Internal Wires
This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access.
Original patent title: “Split memory array to reduce bit-line capacitance”
This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access. Granted in 2026.
Coverage
What does this patent actually cover?
This patent describes a way to improve memory performance by splitting a memory array into two or more smaller sections, called subarrays. It uses special electronic switches, called bit-line multiplexers or selection circuitries, to divide the bit-line routes between these subarrays. By decoupling the bit-lines in this manner, the electrical charge-storing ability, known as capacitance, on the bit-lines is significantly reduced. This reduction comes from decreasing unwanted parasitic capacitance and ensuring that a single bit-line doesn't have to power all the tiny switches (access transistors) in a memory row. For example, when reading data from a specific memory cell, only the relevant split bit-line segment is activated, allowing the electrical signal to develop faster and stronger, which leads to quicker data sensing and overall higher memory performance.
The gap
What does this patent NOT cover?
- Does not cover memory designs that use a single, unbroken bit-line stretching across an entire memory array without splitting.
- Does not cover methods for reducing memory capacitance that do not involve splitting bit-lines with selection circuitries.
- Does not cover improvements to memory speed achieved solely by optimizing access transistor switching without modifying bit-line architecture.
- Does not cover memory architectures that do not rely on bit-lines for data transfer to and from memory cells.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The clever bit is the specific approach of actively decoupling bit-lines into separate routes using multiplexers. This allows for a targeted reduction of parasitic capacitance, ensuring that the main bit-line only drives a smaller portion of the memory array at any given time, which significantly speeds up signal development and sensing.
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Dynamic Random Access Memory (DRAM) modules in computers
Static Random Access Memory (SRAM) caches in processors
NAND flash memory in solid-state drives (SSDs)
Embedded memory in system-on-a-chip (SoC) designs
Why it matters
The bigger picture
The speed of memory directly impacts how fast computers, phones, and other devices can operate. This patent addresses a fundamental physical limitation in memory design: the parasitic capacitance on bit-lines that slows down data access. By reducing this capacitance, the technology described could lead to faster, more power-efficient memory components, which are crucial for everything from high-performance computing to everyday consumer electronics.
Filed
July 12, 2022
Granted
September 15, 2026
Market context
Who's building on this
Companies in this space
Major memory manufacturers like Samsung, Micron Technology, and SK Hynix are continuously researching and developing advanced memory architectures to improve speed and efficiency. Processor designers such as Intel, AMD, and Apple also focus on optimizing integrated memory within their chips. This patent's concepts would be relevant to their ongoing efforts to push the boundaries of memory performance.
Market impact
Improvements in memory performance, like those described in this patent, are critical for the continuous advancement of computing technology. Such innovations help enable faster processing, more responsive devices, and more efficient data centers. While this patent describes a specific technical improvement, it contributes to the broader trend of increasing memory density and speed, which is essential for new generations of smartphones, laptops, and AI hardware.
Claim 1 — Plain English
What this patent covers
This patent describes a way to improve memory performance by splitting a memory array into two or more smaller sections, called subarrays. It uses special electronic switches, called bit-line multiplexers or selection circuitries, to divide the bit-line routes between these subarrays. By decoupling the bit-lines in this manner, the electrical charge-storing ability, known as capacitance, on the bit-lines is significantly reduced. This reduction comes from decreasing unwanted parasitic capacitance and ensuring that a single bit-line doesn't have to power all the tiny switches (access transistors) in a memory row. For example, when reading data from a specific memory cell, only the relevant split bit-line segment is activated, allowing the electrical signal to develop faster and stronger, which leads to quicker data sensing and overall higher memory performance.
The clever bit
The clever bit is the specific approach of actively decoupling bit-lines into separate routes using multiplexers. This allows for a targeted reduction of parasitic capacitance, ensuring that the main bit-line only drives a smaller portion of the memory array at any given time, which significantly speeds up signal development and sensing.
What it does not cover
- Does not cover memory designs that use a single, unbroken bit-line stretching across an entire memory array without splitting.
- Does not cover methods for reducing memory capacitance that do not involve splitting bit-lines with selection circuitries.
- Does not cover improvements to memory speed achieved solely by optimizing access transistor switching without modifying bit-line architecture.
- Does not cover memory architectures that do not rely on bit-lines for data transfer to and from memory cells.
Patent timeline
Application submitted to the patent office
Patent officially issued
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
0/20
Narrow claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
20/20
Granted within 5 years
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$17K – $54K
Midpoint $34K · 15.8 yr remaining · industry ×1.4
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
Concepts involved
Cite this patent
(2026). Making Memory Chips Faster by Splitting Internal Wires (U.S. Patent No. 12,740,066). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/12740066/split-memory-array-to-reduce-bit-line-capacitance
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does Making Memory Chips Faster by Splitting Internal Wires cover?
This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access.
When does this patent expire?
This patent is expected to expire on September 15, 2046, when the invention enters the public domain.
What problem does this patent solve?
The speed of memory directly impacts how fast computers, phones, and other devices can operate. This patent addresses a fundamental physical limitation in memory design: the parasitic capacitance on bit-lines that slows down data access. By reducing this capacitance, the technology described could lead to faster, more power-efficient memory components, which are crucial for everything from high-performance computing to everyday consumer electronics.
What does this patent NOT cover?
Does not cover memory designs that use a single, unbroken bit-line stretching across an entire memory array without splitting.
Patent monitoring