How to Save Memory Power by Grouping Error-Correction Data
A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one.
Original patent title: “Energy efficient storage of error-correction-detection information”
A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one. Granted to Rambus Inc in 2025 with 23 claims.
Key facts
Coverage
What does this patent actually cover?
This patent describes a memory controller that optimizes how it retrieves error-correction information. Traditionally, a controller might trigger a separate row access for every data channel's error-checking bits, which consumes significant power. This design groups check bits for multiple data rows into a single row within an error-correction memory component. When the controller accesses one data row, it simultaneously opens the error-correction row, fetches the necessary check bits, and caches the remaining check bits for future use. This reduces the total number of row activations required to verify data integrity.
The gap
What does this patent NOT cover?
- Does not cover memory systems that use a single channel for both data and error-correction information.
- Does not cover software-based error correction algorithms that run on a CPU.
- Does not cover systems where error-correction bits are stored within the same physical row as the data they protect.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
What made this novel
The innovation lies in pre-fetching and caching 'future' check bits while the error-correction row is already open for a current request, effectively turning one row access into a multi-purpose operation.
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Enterprise server memory controllers
High-performance computing (HPC) memory subsystems
Data center DRAM interfaces
Why it matters
The bigger picture
In large-scale data centers and high-performance computing, memory power consumption is a major operational cost. By reducing the number of row activations—a power-intensive operation—this technology helps lower the thermal and electrical footprint of massive memory arrays. It is particularly relevant for modern server architectures that rely on high-bandwidth, multi-channel memory configurations.
Filed
April 29, 2024
Granted
June 3, 2025
Market context
Who's building on this
Companies in this space
Rambus Inc. remains a primary player in high-speed memory interface design and continues to licenselicensePermission from the patent owner to make, use, or sell the invention — usually in exchange for payment. Doesn't transfer ownership.Read more → these types of architectural optimizations to major DRAM manufacturers and system-on-chip designers.
Market impact
This patent addresses the 'memory wall' problem by improving power efficiency in multi-channel memory systems. It provides a technical pathway for manufacturers to increase memory density and speed without proportional increases in power consumption, which is critical for the scaling of AI and cloud infrastructure.
Claim 1 — Plain English
What this patent covers
This patent describes a memory controller that optimizes how it retrieves error-correction information. Traditionally, a controller might trigger a separate row access for every data channel's error-checking bits, which consumes significant power. This design groups check bits for multiple data rows into a single row within an error-correction memory component. When the controller accesses one data row, it simultaneously opens the error-correction row, fetches the necessary check bits, and caches the remaining check bits for future use. This reduces the total number of row activations required to verify data integrity.
The clever bit
The innovation lies in pre-fetching and caching 'future' check bits while the error-correction row is already open for a current request, effectively turning one row access into a multi-purpose operation.
What it does not cover
- Does not cover memory systems that use a single channel for both data and error-correction information.
- Does not cover software-based error correction algorithms that run on a CPU.
- Does not cover systems where error-correction bits are stored within the same physical row as the data they protect.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
PatentBrief Score
Impact Score
Early stage
Citation count
0/40
No citations yet
Claim breadth
15/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
20/20
Granted within 5 years
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$47K – $150K
Midpoint $94K · 17.9 yr remaining · industry ×1.6
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
The original legal language
Original claims
23 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Magee, S., Miller, M. R., & Linstadt, J. E. (2025). How to Save Memory Power by Grouping Error-Correction Data (U.S. Patent No. 12,321,234). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/12321234/raptor-2
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
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Common Questions
Frequently Asked Questions
What does How to Save Memory Power by Grouping Error-Correction Data cover?
A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one.
Who owns patent US 12321234?
Rambus Inc owns this patent, granted in 2025.
When does this patent expire?
This patent is expected to expire on June 3, 2045, when the invention enters the public domain.
What problem does this patent solve?
In large-scale data centers and high-performance computing, memory power consumption is a major operational cost. By reducing the number of row activations—a power-intensive operation—this technology helps lower the thermal and electrical footprint of massive memory arrays. It is particularly relevant for modern server architectures that rely on high-bandwidth, multi-channel memory configurations.
What does this patent NOT cover?
Does not cover memory systems that use a single channel for both data and error-correction information.
Patent monitoring