How to Save Memory Power by Grouping Error-Correction Data

A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one.

What it covers

This patent describes a memory controller that optimizes how it retrieves error-correction information. Traditionally, a controller might trigger a separate row access for every data channel's error-checking bits, which consumes significant power. This design groups check bits for multiple data rows into a single row within an error-correction memory component. When the controller accesses one data row, it simultaneously opens the error-correction row, fetches the necessary check bits, and caches the remaining check bits for future use. This reduces the total number of row activations required to verify data integrity.

What it doesn't cover

• —Does not cover memory systems that use a single channel for both data and error-correction information.
• —Does not cover software-based error correction algorithms that run on a CPU.
• —Does not cover systems where error-correction bits are stored within the same physical row as the data they protect.

The clever bit

The innovation lies in pre-fetching and caching 'future' check bits while the error-correction row is already open for a current request, effectively turning one row access into a multi-purpose operation.

Why it matters

In large-scale data centers and high-performance computing, memory power consumption is a major operational cost. By reducing the number of row activations—a power-intensive operation—this technology helps lower the thermal and electrical footprint of massive memory arrays. It is particularly relevant for modern server architectures that rely on high-bandwidth, multi-channel memory configurations.

Real-world examples

• 1.Enterprise server memory controllers
• 2.High-performance computing (HPC) memory subsystems
• 3.Data center DRAM interfaces