Making Memory Chips Faster by Splitting Internal Wires

This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access.

What it covers

This patent describes a way to improve memory performance by splitting a memory array into two or more smaller sections, called subarrays. It uses special electronic switches, called bit-line multiplexers or selection circuitries, to divide the bit-line routes between these subarrays. By decoupling the bit-lines in this manner, the electrical charge-storing ability, known as capacitance, on the bit-lines is significantly reduced. This reduction comes from decreasing unwanted parasitic capacitance and ensuring that a single bit-line doesn't have to power all the tiny switches (access transistors) in a memory row. For example, when reading data from a specific memory cell, only the relevant split bit-line segment is activated, allowing the electrical signal to develop faster and stronger, which leads to quicker data sensing and overall higher memory performance.

What it doesn't cover

• —Does not cover memory designs that use a single, unbroken bit-line stretching across an entire memory array without splitting.
• —Does not cover methods for reducing memory capacitance that do not involve splitting bit-lines with selection circuitries.
• —Does not cover improvements to memory speed achieved solely by optimizing access transistor switching without modifying bit-line architecture.
• —Does not cover memory architectures that do not rely on bit-lines for data transfer to and from memory cells.

The clever bit

The clever bit is the specific approach of actively decoupling bit-lines into separate routes using multiplexers. This allows for a targeted reduction of parasitic capacitance, ensuring that the main bit-line only drives a smaller portion of the memory array at any given time, which significantly speeds up signal development and sensing.

Why it matters

The speed of memory directly impacts how fast computers, phones, and other devices can operate. This patent addresses a fundamental physical limitation in memory design: the parasitic capacitance on bit-lines that slows down data access. By reducing this capacitance, the technology described could lead to faster, more power-efficient memory components, which are crucial for everything from high-performance computing to everyday consumer electronics.

Real-world examples

• 1.Dynamic Random Access Memory (DRAM) modules in computers
• 2.Static Random Access Memory (SRAM) caches in processors
• 3.NAND flash memory in solid-state drives (SSDs)
• 4.Embedded memory in system-on-a-chip (SoC) designs