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How Chips Save Power by Managing Individual Parts Separately

A method for computer chips to save energy by monitoring how busy specific internal parts are and adjusting their power and speed individually rather than as a whole.

Granted 2019ActiveExpires 2036Owned by Advanced Micro Devices IncInvented by Evandro Menezes, Morrie Altmejd, Dave Tobias

Original patent title: “USRE47420E1 - Performance and power optimization via block oriented performance measurement and control

Plain-English explanation by SahiLast reviewed · June 15, 2026

A method for computer chips to save energy by monitoring how busy specific internal parts are and adjusting their power and speed individually rather than as a whole. Granted to Advanced Micro Devices Inc in 2019 with 54 claims and 1 forward citation.

Key facts

Patent numberUS RE47420
StatusActive
FieldSemiconductors & Chips
AssigneeAdvanced Micro Devices Inc
InventorsEvandro Menezes, Morrie Altmejd, Dave Tobias
Filed2016
Granted2019
Claims54
Times cited1
LitigationNone on record
Value · $96K$307KModest

Coverage

What does this patent actually cover?

Modern computer chips are made of many specialized sections, like math units or memory controllers. This patent describes a system where each of these sections reports how busy it is—its utilization level—to a central controller. Instead of slowing down the entire chip when the workload is light, the system independently adjusts the voltage, clock speed, or operation dispatch rate for only the busy or idle sections. For example, if a chip is processing complex math but not using its input/output interface, the math unit can run at high speed while the interface is throttled down to save battery.

The gap

What does this patent NOT cover?

  • Does not cover power management schemes that treat the entire processor as a single unit.
  • Does not cover software-only power management that lacks hardware-level utilization monitoring circuits.
  • Does not cover power adjustments based on external factors like temperature or ambient light.

These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.

What made this novel

The innovation lies in the granularity of the control: by using utilization registers to track activity at the level of specific functional blocks, the chip can make micro-adjustments in real-time that are invisible to the user but significant for energy efficiency.

USRE47420E1 - Performance and …(Primary claim)semiconductorsconsumer electronics

Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.

Where you've seen this

Real-world examples

01

AMD Ryzen mobile processors

02

Modern laptop CPUs with dynamic frequency scaling

03

Smartphone system-on-a-chip (SoC) power management

Why it matters

The bigger picture

This technology is fundamental to modern mobile and high-performance computing. As chips get denser, managing heat and battery life becomes impossible if you treat the whole chip as one power domain. This approach allows devices like laptops and smartphones to deliver high performance when needed while remaining efficient during background tasks.

Filed

July 22, 2016

Granted

June 4, 2019

Market context

Who's building on this

Companies in this space

Advanced Micro Devices (AMD) continues to refine this technology in their Zen architecture series. Other major chip designers like Intel and ARM utilize similar granular power management techniques to balance performance and thermal constraints in their respective architectures.

Market impact

This approach to power management has become an industry standard for mobile and server-grade silicon. It enabled the transition to highly efficient multi-core processors, allowing manufacturers to pack more transistors onto a chip without exceeding the thermal limits of the device.

Claim 1 — Plain English

What this patent covers

Modern computer chips are made of many specialized sections, like math units or memory controllers. This patent describes a system where each of these sections reports how busy it is—its utilization level—to a central controller. Instead of slowing down the entire chip when the workload is light, the system independently adjusts the voltage, clock speed, or operation dispatch rate for only the busy or idle sections. For example, if a chip is processing complex math but not using its input/output interface, the math unit can run at high speed while the interface is throttled down to save battery.

The clever bit

The innovation lies in the granularity of the control: by using utilization registers to track activity at the level of specific functional blocks, the chip can make micro-adjustments in real-time that are invisible to the user but significant for energy efficiency.

What it does not cover

  • Does not cover power management schemes that treat the entire processor as a single unit.
  • Does not cover software-only power management that lacks hardware-level utilization monitoring circuits.
  • Does not cover power adjustments based on external factors like temperature or ambient light.

Patent timeline

Filing

Application submitted to the patent office

Publication

Application published, typically 18 months after filing

Grant

Patent officially issued

PatentBrief Score

Impact Score

Early stage

Citation count

6/40

Early citations

Claim breadth

20/20

Very broad protection

Recency

10/20

Granted 5–10 years ago

Assignee scale

0/20

Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →

PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.

Heuristic Value Estimate

What this patent might be worth

Modest

$96K$307K

Midpoint $192K · 10.1 yr remaining · industry ×1.6

Adjust inputs →

Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.

The original legal language

Original claims

54 claims as filed with the patent office.

Concepts involved

ClaimPrior artNon-obviousnessNoveltySpecificationAssigneePatent term

Citations

Patent lineage

Cites earlier patents

268

earlier patents this invention cites as foundations

View prior art →

Cited by later patents

1

later patents that build on this invention

View patents →

Cite this patent

Menezes, E., Altmejd, M., & Tobias, D. (2019). How Chips Save Power by Managing Individual Parts Separately (U.S. Patent No. RE47,420). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/RE47420/google-translate

Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.

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Common Questions

Frequently Asked Questions

What does How Chips Save Power by Managing Individual Parts Separately cover?

A method for computer chips to save energy by monitoring how busy specific internal parts are and adjusting their power and speed individually rather than as a whole.

Who owns patent US RE47420?

Advanced Micro Devices Inc owns this patent, granted in 2019.

When does this patent expire?

This patent is expected to expire on June 4, 2039, when the invention enters the public domain.

What is patent US RE47420 cited by?

This patent has been cited by 1 later patents that build on its ideas.

What problem does this patent solve?

This technology is fundamental to modern mobile and high-performance computing. As chips get denser, managing heat and battery life becomes impossible if you treat the whole chip as one power domain. This approach allows devices like laptops and smartphones to deliver high performance when needed while remaining efficient during background tasks.

What does this patent NOT cover?

Does not cover power management schemes that treat the entire processor as a single unit.

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Last reviewed: June 15, 2026 · PatentBrief is not a law firm and this is not legal advice.