How Asynchronous Buffers Speed Up Non-Volatile Memory Access
This patent describes a non-volatile storage device that uses a special buffer, called an asynchronous FIFO, to quickly deliver data from memory by handling read and write operations with different timing signals and pre-fetching data.
Original patent title: “Asynchronous FIFO buffer for memory access”
This patent describes a non-volatile storage device that uses a special buffer, called an asynchronous FIFO, to quickly deliver data from memory by handling read and write operations with different timing signals and pre-fetching data. Granted to SanDisk Technologies in 2016 with 20 claims and 7 forward citations, and it is expected to expire in 2034.
Coverage
What does this patent actually cover?
This patent describes a non-volatile storage device, like a flash drive, that uses an asynchronous first-in first-out (FIFO) buffer to manage data flow. The device has a memory array (ClaimclaimA numbered sentence at the end of a patent that legally defines what the inventor owns. The most important section.Read more → 1) and a data interface for outputting information. A 'read enable signal' tells the device how to clock data out (Claim 1). The clever part is the asynchronous FIFO buffer, which has separate clock inputs: a 'read clock input' receives the read enable signal, and a 'write clock input' receives a 'write clock' that is a *delayed and asynchronous* version of the read enable signal (Claim 1). This means the buffer can take data from the memory array at one speed and output it at another, independent speed. For example, when you request data from an SSD, the control logic can pre-fetch data into this FIFO buffer *before* your computer even starts asking for it, ensuring it's ready to be clocked out immediately (Claim 6, 8).
The gap
What does this patent NOT cover?
- Does not cover synchronous FIFO buffers where read and write operations are tied to the same clock signal.
- Does not cover memory systems that do not employ a separate, delayed, and asynchronous write clock for the FIFO buffer.
- Does not cover systems that do not pre-fetch data into the FIFO buffer prior to the initial read enable signal.
- Does not cover volatile memory types like DRAM, as the claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more → specifically refer to a 'non-volatile storage device'.
- Does not cover data transfer methods that do not use a FIFO buffer as an intermediary between the memory array and the data interface.
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
Key facts
What made this novel
The truly novel aspect is using an asynchronous FIFO buffer with a write clock that is a *delayed and asynchronous* version of the read enable signal, combined with pre-fetching data into this buffer. This allows the system to prepare data for output ahead of time, minimizing delays caused by different clock speeds between the memory and the system requesting data.
The Patent Drawing
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
Solid-state drives (SSDs)
USB flash drives
eMMC storage in smartphones and tablets
NVMe storage devices
Memory controllers in enterprise storage arrays
Why it matters
The bigger picture
Modern computing relies heavily on fast access to stored data. Non-volatile storage devices, like SSDs, need to deliver data quickly and efficiently to keep up with processors. This patent improves data delivery by intelligently buffering data, reducing latency and ensuring a smooth flow even when the memory array and the requesting device operate at different speeds. This is crucial for the performance of everything from smartphones to data centers.
Filed
February 28, 2014
Granted
August 9, 2016
Market context
Who's building on this
Companies in this space
SanDisk Technologies LLC, the original assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →, continues to be a major player in non-volatile memory, particularly flash memory and SSDs. Companies like Western Digital (which acquired SanDisk), Samsung, Micron, and SK Hynix are constantly innovating in memory controller design and data buffering techniques to optimize performance in their SSDs and other storage products.
Market impact
This patent contributed to the ongoing effort to reduce latency and increase throughput in non-volatile storage devices. By enabling more efficient data transfer between memory arrays and host systems, it supported the development of faster SSDs and other flash-based storage solutions. This efficiency is critical for modern computing, where quick data access directly impacts user experience and system performance across various devices.
Claim 1 — Plain English
What this patent covers
This patent describes a non-volatile storage device, like a flash drive, that uses an asynchronous first-in first-out (FIFO) buffer to manage data flow. The device has a memory array (Claim 1) and a data interface for outputting information. A 'read enable signal' tells the device how to clock data out (Claim 1). The clever part is the asynchronous FIFO buffer, which has separate clock inputs: a 'read clock input' receives the read enable signal, and a 'write clock input' receives a 'write clock' that is a *delayed and asynchronous* version of the read enable signal (Claim 1). This means the buffer can take data from the memory array at one speed and output it at another, independent speed. For example, when you request data from an SSD, the control logic can pre-fetch data into this FIFO buffer *before* your computer even starts asking for it, ensuring it's ready to be clocked out immediately (Claim 6, 8).
The clever bit
The truly novel aspect is using an asynchronous FIFO buffer with a write clock that is a *delayed and asynchronous* version of the read enable signal, combined with pre-fetching data into this buffer. This allows the system to prepare data for output ahead of time, minimizing delays caused by different clock speeds between the memory and the system requesting data.
What it does not cover
- Does not cover synchronous FIFO buffers where read and write operations are tied to the same clock signal.
- Does not cover memory systems that do not employ a separate, delayed, and asynchronous write clock for the FIFO buffer.
- Does not cover systems that do not pre-fetch data into the FIFO buffer prior to the initial read enable signal.
- Does not cover volatile memory types like DRAM, as the claims specifically refer to a 'non-volatile storage device'.
- Does not cover data transfer methods that do not use a FIFO buffer as an intermediary between the memory array and the data interface.
Patent timeline
Application submitted to the patent office
Application published, typically 18 months after filing
Patent officially issued
Patent enters public domain
PatentBrief Score
Impact Score
Moderate
Citation count
18/40
Early citations
Claim breadth
13/20
Broad claimsclaimsThe numbered statements at the end of a patent that legally define what the inventor owns.Read more →
Recency
10/20
Granted 5–10 years ago
Assignee scale
0/20
Independent or smaller assigneeassigneeThe entity that owns the patent — usually the inventor's employer or a company.Read more →
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Heuristic Value Estimate
What this patent might be worth
$100K – $319K
Midpoint $200K · 7.6 yr remaining · industry ×1.6
Heuristic only — blends forward/backward citation counts, claim scope, time remaining, litigation history, and CPC-derived industry baseline. Real valuations need a professional appraisal.
Claim text not yet imported for this patent
The original legal language
Original claims
20 claims as filed with the patent office.
Concepts involved
Citations
Patent lineage
Cite this patent
Yap, K. A. (2016). How Asynchronous Buffers Speed Up Non-Volatile Memory Access (U.S. Patent No. 9,411,722). U.S. Patent and Trademark Office. https://patentbrief.org/patent/us/9411722/asynchronous-fifo-buffer-for-memory-access
Auto-generated from the patent record. Double-check author order and the issue date against the official USPTO document before submitting.
Embed
Add this patent to your site
Drop this plain-English patent card into any blog post or article — free, no signup. It always links back to the full breakdown here.
<div data-patentlens-widget data-patent-number="US9411722"></div> <script src="https://patentbrief.org/embed.js" async></script>
Stay in the loop
Get a weekly digest of new patents.
One email per week. No spam. Unsubscribe anytime.
Keep exploring
Related patents you should know
US 4683195 · 1987
How to Make Billions of Copies of a DNA Segment
This patent describes the Polymerase Chain Reaction (PCR), a method to rapidly create many copies of a specific piece of DNA or RNA, enabling its detection and analysis.
Cetus Corp
US 8697359 · 2014
How to Edit Genes in Human Cells Using an Engineered CRISPR System
This patent describes an engineered CRISPR-Cas9 system for precisely cutting DNA in eukaryotic cells to change how genes work, opening the door for gene editing in complex organisms.
Massachusetts Institute of Technology
US 7657849 · 2010
How the iPhone's Slide-to-Unlock Gesture Works
Apple's 2010 patent describes unlocking a device by dragging a specific graphical image across the touchscreen along a predefined path, a gesture that became iconic with the original iPhone.
Apple Inc
US 4733665 · 1988
How Doctors Implant a Permanent Stent Using a Balloon
This patent describes the method for placing a permanent, expandable wire mesh tube inside a blood vessel or other body tube using a balloon-tipped catheter to widen it and keep it open.
Expandable Grafts Partnership
US 4965188 · 1990
How to Make Many Copies of a DNA Piece with Heat
This patent describes the Polymerase Chain Reaction (PCR) method, a technique to make millions of copies of a specific DNA segment using a heat-resistant enzyme and repeated temperature changes.
Cetus Corp
US 4235871 · 1980
How to Encapsulate Active Materials in Lipid Bubbles Efficiently
This patent describes a method for trapping biologically active substances inside tiny, multi-layered fat bubbles called liposomes, using a specific water-in-oil emulsion and gel-forming process to improve how much material gets captured.
Individual
Semantically similar
You might also find these interesting
US 11593031 · 2023 · Samsung Electronics Co
How Devices Use 'Credits' to Manage Data Flow to Storage
US 10019188 · 2018 · Samsung Electronics Co
How NAND Flash Memory Adjusts to Cold Temperatures
US 5903495 · 1999 · Toshiba Corp
How Multi-Level Cell Memory Stores More Data in Less Space
US 5682513 · 1997 · International Business Machines Corp
How IBM's Storage Controllers Keep Data Backups in the Right Order
More to explore
More in Consumer Electronics
US 7657849 · 2010 · Apple Inc
How the iPhone's Slide-to-Unlock Gesture Works
US 7479949 · 2009 · Apple Inc
How Touchscreens Understand Your Finger Swipes and Scrolls
US 4528643 · 1985 · FPDC Inc
How Stores Make Custom Products On-Demand with Remote Approval
US 7469381 · 2008 · Apple Inc
How Touchscreens Show and Snap Back When You Scroll Past an Edge
New to patents?
Common Questions
Frequently Asked Questions
What does How Asynchronous Buffers Speed Up Non-Volatile Memory Access cover?
This patent describes a non-volatile storage device that uses a special buffer, called an asynchronous FIFO, to quickly deliver data from memory by handling read and write operations with different timing signals and pre-fetching data.
Who owns patent US 9411722?
SanDisk Technologies owns this patent, granted in 2016.
When does this patent expire?
This patent is expected to expire on February 28, 2034, when the invention enters the public domain.
What is patent US 9411722 cited by?
This patent has been cited by 7 later patents that build on its ideas.
What problem does this patent solve?
Modern computing relies heavily on fast access to stored data. Non-volatile storage devices, like SSDs, need to deliver data quickly and efficiently to keep up with processors. This patent improves data delivery by intelligently buffering data, reducing latency and ensuring a smooth flow even when the memory array and the requesting device operate at different speeds. This is crucial for the performance of everything from smartphones to data centers.
What does this patent NOT cover?
Does not cover synchronous FIFO buffers where read and write operations are tied to the same clock signal.
Patent monitoring