GaN Power Semiconductor Patents

Gallium nitride (GaN) power patents cover GaN HEMT device-structure innovations; enhancement-mode (normally-off) gate innovations; epitaxy and substrate innovations; and monolithic-integration and reliability innovations — with IP held by GaN-pure-play startups, integration specialists, and power-semiconductor giants. MAJOR GaN POWER PATENT HOLDERS: EPC (Efficient Power Conversion): eGaN enhancement-mode GaN-on-silicon FETs (chip-scale, the early commercial e-mode leader), and a foundational e-mode portfolio. NAVITAS SEMICONDUCTOR: GaNFast monolithically-integrated GaN power ICs (GaN FET + gate driver + protection on one die — the key fast-charger enabler), GaNSense current sensing. INFINEON: CoolGaN (p-GaN gate enhancement-mode), and it acquired GaN Systems (embedded-die packaging, automotive) — consolidating a large GaN estate. TRANSPHORM: high-voltage normally-off via a cascode (depletion-mode GaN HEMT + low-voltage silicon MOSFET in series), 650 V automotive/industrial. OTHERS: Power Integrations (PowiGaN, integrated switchers), Texas Instruments (integrated GaN), Nexperia (GaN FET), Innoscience (8-inch GaN-on-Si, high-volume, China — also in IP litigation with Infineon/EPC), STMicroelectronics, and RF-GaN heritage holders (the AlGaN/GaN HEMT traces to defense/RF work). Enhancement-mode gate technology and monolithic integration are the most distinctive GaN power patent domains.

GaN HEMT heterostructure innovations; enhancement-mode gate innovations; cascode and hybrid innovations; and lateral/vertical-device innovations represent core GaN power patent domains — and achieving a reliable normally-off device is the central GaN power challenge. HEMT-STRUCTURE PATENTS: the AlGaN/GaN high-electron-mobility transistor — a two-dimensional electron gas 2DEG formed at the heterointerface by spontaneous/piezoelectric polarization (no doping needed), with field plates to manage peak fields and enable high breakdown, ohmic-contact and access-region design, and surface passivation. ENHANCEMENT-MODE (NORMALLY-OFF) PATENTS: the as-grown GaN HEMT is depletion-mode (normally-on, unsafe for power), so making it normally-off is the key IP — p-GaN gate (a p-type GaN cap that depletes the 2DEG at zero bias — Infineon CoolGaN, EPC, Innoscience), recessed-gate/gate-injection transistor GIT, and fluorine-treatment approaches; the p-GaN gate is the dominant commercial e-mode method and a dense patent area. CASCODE / HYBRID PATENTS: cascode configuration (a normally-on GaN HEMT in series with a low-voltage silicon MOSFET to present a normally-off device with a standard gate drive — Transphorm), and co-packaging. LATERAL / VERTICAL PATENTS: lateral GaN (today's commercial structure, on a Si or SiC handle) versus vertical GaN (current flows through the substrate for higher voltage/current density — the emerging frontier needing bulk-GaN substrates). The enhancement-mode gate (especially p-GaN) and emerging vertical GaN are the highest-value device IP.

GaN-on-silicon/SiC epitaxy innovations; monolithic-integration innovations; dynamic-on-resistance and reliability innovations; and packaging innovations represent additional GaN power patent domains. EPITAXY / SUBSTRATE PATENTS: GaN-on-silicon growth (cheap large-diameter Si handle — 150/200 mm, enabling low cost, but requiring stress/buffer engineering for the GaN/Si lattice and thermal mismatch — strain-relief buffer layers, carbon doping for buffer isolation), GaN-on-SiC (better thermal, used in RF/high-perf), GaN-on-GaN bulk substrates (for vertical devices), and defect/dislocation management. MONOLITHIC-INTEGRATION PATENTS: integrating the GaN FET with its gate driver, level-shifters, protection, and even logic on one GaN die or co-packaged (Navitas GaNFast, TI, Power Integrations) — GaN's lateral structure makes monolithic half-bridges and driver integration feasible, a major differentiator versus discrete silicon. RELIABILITY PATENTS: dynamic on-resistance (current collapse — trapped charge raising Rdson after switching, the historic GaN reliability problem) mitigation via field plates, passivation, and buffer engineering; gate reliability and threshold stability; and short-circuit/avalanche robustness. PACKAGING PATENTS: chip-scale/embedded-die packaging, low-inductance layouts (to exploit GaN's very fast switching), and thermal management. Monolithic integration (driver + FET) and dynamic-Rdson reliability are the highest-value GaN power IP because they enable GaN's small, fast, integrated value proposition in chargers and data-center power.

GaN power startup IP strategy must navigate EPC and Infineon (CoolGaN + acquired GaN Systems) e-mode and packaging estates, Navitas monolithic-integration patents, Transphorm cascode patents, active GaN patent litigation (Infineon, EPC, Innoscience and others have litigated e-mode and packaging IP), foundry/epitaxy dependencies (many fabless GaN players rely on TSMC/foundry GaN-on-Si), and automotive qualification; understand that p-GaN-gate enhancement-mode and monolithic integration are densely patented and litigated, that the durable IP for a startup is usually a specific e-mode gate technique, a novel epitaxy/buffer for GaN-on-Si, a monolithic-integration or driver design, or a vertical-GaN structure, and that GaN competes with SiC (GaN for higher-frequency lower-voltage, SiC for higher-voltage/current); identify whitespace in vertical GaN, advanced integration, dynamic-Rdson reliability, and higher-voltage (>650 V) GaN. GaN POWER STARTUP IP STRATEGY: E-MODE GATE AND INTEGRATION ARE LITIGATED — VERTICAL GaN, EPITAXY, AND RELIABILITY ARE OPENINGS: p-GaN-gate e-mode and monolithic integration are densely patented and actively litigated (Infineon/EPC/Innoscience) — patent a specific e-mode technique, a novel GaN-on-Si buffer/epitaxy, a monolithic-driver design, or a vertical-GaN structure; VERTICAL GaN AND >650V ARE HIGHEST-VALUE WHITESPACE: today's commercial GaN is lateral and ≤650 V; vertical GaN (on bulk-GaN substrates) for higher voltage/current density is the frontier and least-consolidated; MONOLITHIC INTEGRATION IS GaN'S KILLER ADVANTAGE: GaN's lateral structure enables FET+driver+protection on one die (Navitas-style) — integration and driver IP are highly defensible and valuable; DYNAMIC-Rdson RELIABILITY IS OPEN TECHNICAL TERRAIN: current-collapse mitigation (field plates, passivation, buffer) is patentable and still being solved; POSITION VS SiC, NOT AGAINST IT: GaN wins high-frequency/lower-voltage (chargers, data center, LiDAR, RF); SiC wins high-voltage/traction — patent for GaN's sweet spot; WHEN TO PATENT: NOVEL DEVICE/PROCESS WITH MEASURED PERFORMANCE: file once a device shows measured results (on-resistance mΩ + dynamic-Rdson ratio + switching frequency + breakdown V + integration level + reliability hours) vs. EPC/Navitas/Infineon baselines — measured on-resistance, dynamic-Rdson, switching frequency, breakdown voltage, and integration are the critical GaN IP metrics; KEY FTO CHECKLIST: EPC eGaN enhancement-mode chip-scale; Navitas GaNFast monolithic FET+driver GaNSense; Infineon CoolGaN p-GaN gate + GaN Systems embedded-die; Transphorm cascode D-mode GaN + Si MOSFET; Innoscience 8-inch GaN-on-Si (litigated); p-GaN gate vs recessed-gate GIT vs fluorine e-mode; AlGaN/GaN 2DEG field-plate passivation; GaN-on-Si buffer/carbon-doping stress; vertical GaN bulk substrate; dynamic-Rdson current-collapse; AEC-Q automotive.