Silicon Carbide Power Patents

Silicon carbide (SiC) power patents cover substrate-crystal-growth innovations; SiC MOSFET device-structure innovations; gate-oxide and reliability innovations; and module-packaging innovations — with IP held by the substrate-and-device leader, European and Japanese power-semiconductor giants, and EV-supply specialists. MAJOR SiC POWER PATENT HOLDERS: WOLFSPEED (formerly Cree, the SiC pioneer): SiC substrate (boule) growth and the 150 mm → 200 mm wafer transition, SiC MOSFETs and Schottky diodes, and the vertically-integrated leader in SiC materials — Wolfspeed's substrate IP and capacity underpin much of the industry (many device makers buy or license its wafers). INFINEON: CoolSiC trench MOSFETs (.XT packaging, automotive-qualified), and a broad power-device estate. STMICROELECTRONICS: planar SiC MOSFETs (a major Tesla Model 3 inverter supplier), and growing in-house substrate capability. ROHM: trench SiC MOSFETs (early trench commercialization). ONSEMI: EliteSiC (substrate + device, vertically integrated after GTAT acquisition). OTHERS: Mitsubishi Electric, Bosch (in-house SiC fab for automotive), Toshiba, Renesas, and substrate specialists (Coherent/II-VI, SK Siltron, SiCrystal/Rohm, Soitec SmartSiC engineered substrates). SiC substrate growth and trench-MOSFET device structure are the most strategically important SiC patent domains.

Crystal-growth (boule) innovations; defect-reduction innovations; wafer-diameter-scaling innovations; and epitaxy and wafering innovations represent core SiC substrate patent domains — and substrate is the cost and supply bottleneck of the whole SiC industry. CRYSTAL-GROWTH PATENTS: physical vapor transport PVT (sublimation) growth of 4H-SiC boules (seed, sublimation, thermal-gradient control), high-temperature solution growth, and emerging higher-throughput methods — crystal quality and growth rate are the key levers. DEFECT-REDUCTION PATENTS: elimination/reduction of micropipes (the historic killer defect), basal-plane dislocations BPDs (which cause bipolar degradation in devices), threading dislocations, and stacking faults — defect density directly determines device yield and reliability, so defect-reduction methods are extremely valuable. WAFER-SCALING PATENTS: the 150 mm to 200 mm diameter transition (larger wafers cut cost per die), warp/bow and stress management at larger diameters, and n-type doping uniformity. EPITAXY / WAFERING PATENTS: SiC epitaxial-layer growth (thickness/doping control for the drift region), engineered/bonded substrates (Soitec SmartSiC — a thin SiC layer on a lower-grade poly-SiC handle to save material), laser-assisted slicing (cold split) to reduce kerf loss, and surface finishing. Substrate growth, defect reduction, and 200 mm scaling are the highest-strategic-value SiC IP because substrate is ~50% of device cost and the industry's supply constraint.

SiC MOSFET device-structure innovations; gate-oxide and channel-reliability innovations; body-diode and short-circuit innovations; and module-packaging innovations represent additional SiC power patent domains. DEVICE-STRUCTURE PATENTS: planar (DMOS) versus trench (UMOS) SiC MOSFET architectures (trench gives lower on-resistance/area but harder reliability), double-trench and shielded-trench designs to protect the gate oxide from high fields, JFET-region and cell-pitch optimization, and superjunction/charge-balance concepts. GATE-OXIDE / RELIABILITY PATENTS: the SiC/SiO2 interface is the central SiC reliability challenge — nitridation and interface-trap reduction (improving channel mobility and threshold stability), gate-oxide field shielding, and threshold-voltage stability/hysteresis mitigation. BODY-DIODE / ROBUSTNESS PATENTS: intrinsic body-diode bipolar-degradation mitigation (BPD-related), short-circuit withstand-time, avalanche ruggedness, and surge capability. MODULE-PACKAGING PATENTS: low-inductance power-module layouts (critical to exploit SiC's fast switching), silver-sinter and transient-liquid-phase die attach, double-sided cooling, copper clip/wire-bond-less interconnect, and high-temperature substrates (AMB ceramic). Trench-MOSFET structure with a reliable, shielded gate oxide, plus low-inductance modules, are the highest-value SiC device IP because they determine on-resistance, switching loss, and reliability in EV traction inverters.

Silicon carbide power startup IP strategy must navigate Wolfspeed's deep substrate and device estate (and its central role as a wafer supplier), Infineon/ST/ROHM/onsemi trench-MOSFET and packaging portfolios, substrate-specialist patents (Coherent, Soitec engineered substrates), high capital intensity (a SiC fab/substrate line is enormously expensive), automotive qualification (AEC-Q101) requirements, and a landscape where substrate supply and device reliability are the gating issues; understand that substrate growth and trench-MOSFET structures are densely patented by incumbents, that the durable IP for a newcomer is usually a specific defect-reduction or growth method, an engineered/bonded-substrate approach, a novel device structure, or module packaging, and that capital and qualification are as decisive as IP; identify whitespace in engineered substrates (material-saving), defect reduction, novel gate-oxide reliability, and advanced packaging. SiC STARTUP IP STRATEGY: SUBSTRATE AND TRENCH-MOSFET ARE INCUMBENT-DENSE — DEFECT REDUCTION, ENGINEERED SUBSTRATES, AND PACKAGING ARE THE OPENINGS: Wolfspeed/Infineon/ST/ROHM hold deep substrate and device IP — patent a specific defect-reduction/growth method, an engineered/bonded-substrate (SmartSiC-style material saving), a novel gate-oxide/channel reliability technique, or low-inductance packaging; SUBSTRATE COST/SUPPLY IS THE INDUSTRY BOTTLENECK — MATERIAL-SAVING IS HIGHEST-VALUE: substrate is ~half of device cost; engineered substrates, larger-diameter (200 mm) scaling, and kerf-loss-reduction (cold-split slicing) are the most commercially decisive whitespace; GATE-OXIDE RELIABILITY AND BPD MITIGATION ARE OPEN TECHNICAL TERRAIN: the SiC/SiO2 interface and body-diode bipolar degradation are unsolved enough to patent around; CAPITAL AND AEC-Q QUALIFICATION ARE PARALLEL MOATS: SiC is capital-intensive and automotive-qualification-gated — IP without a fab/foundry and qualification plan is incomplete; WHEN TO PATENT: NOVEL MATERIAL/DEVICE WITH MEASURED PERFORMANCE: file once a process/device shows measured results (defect density cm⁻² + on-resistance mΩ·cm² + switching loss + gate-oxide lifetime + yield) vs. Wolfspeed/Infineon baselines — measured defect density, specific on-resistance, switching loss, reliability lifetime, and yield are the critical SiC IP metrics; KEY FTO CHECKLIST: Wolfspeed PVT boule 150/200mm substrate + MOSFET; Infineon CoolSiC trench .XT; ST planar SiC MOSFET; ROHM trench double-trench; onsemi EliteSiC; Soitec SmartSiC engineered/bonded substrate; PVT growth micropipe/BPD defect reduction; SiC/SiO2 nitridation gate-oxide interface-trap; shielded-trench field protection; body-diode bipolar-degradation; silver-sinter low-inductance double-sided-cooled module; AEC-Q101 qualification.