EUV Lithography Patents

EUV lithography patents cover light-source innovations; optics/mirror innovations; mask/pellicle innovations; and resist/process and system/high-NA innovations — with IP held by semiconductor-equipment and materials companies and research organizations (in a field of advanced semiconductor patterning). WHY EUV LITHOGRAPHY: 'EUV LITHOGRAPHY' (extreme ultraviolet lithography) is the technology that prints the TINIEST features on the most advanced semiconductor chips, using light at a 13.5 nm WAVELENGTH (extreme ultraviolet) — far shorter than the 193 nm deep-UV light used before — enabling the patterning of the smallest transistors at leading-edge NODES (5nm, 3nm, and below); EUV is one of the most COMPLEX machines humanity has built, and a profound technical achievement: because EVERYTHING ABSORBS 13.5 nm light (including air, glass, and most materials), EUV must work in a VACUUM and use REFLECTIVE optics (precision MULTILAYER MIRRORS) instead of lenses, and the light is generated by an extraordinary process — blasting tiny droplets of molten TIN with a high-power LASER ~50,000 times per second to create a PLASMA that emits the 13.5 nm light; ASML is the SOLE maker of EUV scanners (with Zeiss optics and Cymer/ASML light sources), making it one of the most strategically critical (and IP-DENSE) technologies in the world; the brutal CHALLENGES: the LIGHT SOURCE (generating enough EUV POWER/throughput cheaply — historically the biggest BOTTLENECK), the OPTICS (defect-free multilayer mirrors with extreme precision and reflectivity), the MASK and PELLICLE (defect-free reflective masks, and a thin PELLICLE membrane that protects the mask while surviving the EUV power — a hard materials problem), the PHOTORESIST (light-sensitive material with the resolution, sensitivity, and low-defect performance — including new metal-oxide/EUV resists), and the overall SYSTEM (and the next step, HIGH-NA EUV for even smaller features); the make-or-break IP AREAS: the LIGHT SOURCE, the OPTICS/mirror, the MASK/pellicle, the RESIST/process, and system/high-NA; the HARD problems: the LIGHT-SOURCE, OPTICS/mirror, MASK/pellicle, RESIST/process, and system/high-NA. MAJOR PLAYERS: ASML, ZEISS, CYMER, plus semiconductor-equipment and materials companies. Light-source, optics/mirror, mask/pellicle, resist/process, and system/high-NA are the core EUV-lithography patent domains — and light source, optics, mask/pellicle, resist, and system are the open whitespace. (Note: EUV lithography prints the smallest chip features using 13.5 nm light — requiring vacuum, reflective multilayer-mirror optics, and a laser-produced tin-plasma light source; it is one of the most complex, IP-dense, strategically critical technologies (ASML/Zeiss/Cymer), with brutal challenges in source POWER, defect-free OPTICS/MASKS/PELLICLES, and PHOTORESIST (stochastics), plus HIGH-NA; it is semiconductor-equipment/optics/materials IP strongly §101-resilient.)

Light-source innovations; optics/mirror innovations; tin-plasma-source innovations; and multilayer-mirror innovations represent core EUV-lithography patent domains — and the light source (the historical bottleneck) and the optics/mirrors (the reflective path) are the foundational, high-value, §101-resilient capabilities. LIGHT-SOURCE PATENTS: the EUV LIGHT — generating 13.5 nm EUV by LASER-PRODUCED TIN PLASMA (blasting molten-TIN DROPLETS with a high-power CO2 laser ~50,000×/second to create a plasma emitting EUV), source POWER/THROUGHPUT (the HISTORICAL BOTTLENECK — more EUV power = more wafers/hour = better economics — getting to high power was the key enabler), DROPLET GENERATION (precise tin droplets), COLLECTOR OPTICS (capturing the emitted EUV), and DEBRIS management/CONVERSION EFFICIENCY (tin debris fouls optics; converting laser energy to EUV efficiently); light-source methods are core, high-value, DISTINCTIVE IP, §101-resilient (the source/plasma is technical — strong IP) — the EUV LIGHT SOURCE (laser-produced tin plasma, source POWER/throughput, droplet/collector, debris/conversion) is core, contested, defensible IP, since the source power was the central bottleneck and determines throughput/economics. OPTICS / MIRROR PATENTS: the REFLECTIVE PATH — precision REFLECTIVE OPTICS (since everything absorbs EUV, the system uses mirrors, not lenses), MULTILAYER MIRRORS (alternating molybdenum/silicon (Mo/Si) nanolayers that reflect 13.5 nm by interference — extraordinary precision/reflectivity), DEFECT-FREE/FIGURE PRECISION (atomic-level surface figure), and REFLECTIVITY; optics/mirror methods are core, high-value, DISTINCTIVE IP, §101-resilient (the REFLECTIVE OPTICS and MULTILAYER MIRRORS (Mo/Si, atomic precision, reflectivity) are core, contested, defensible IP — Zeiss's domain — since EUV's reflective optics are an extreme precision achievement). TIN-PLASMA-SOURCE PATENTS: laser-produced tin-plasma EUV generation; tin-plasma-source methods are high-value IP, §101-resilient (tin-plasma is the EUV source technology — power/efficiency the key). MULTILAYER-MIRROR PATENTS: Mo/Si EUV reflective mirrors; multilayer-mirror methods are high-value IP (multilayer mirrors enable reflective EUV optics — extreme precision). Light-source, optics/mirror, tin-plasma-source, and multilayer-mirror are the highest-value core IP because the EUV source (power) and the reflective multilayer-mirror optics are exactly what make EUV lithography possible.

Mask/pellicle innovations; resist/process innovations; system/high-NA innovations; and EUV-pellicle innovations represent additional EUV-lithography patent domains — and the mask/pellicle, the resist/process, and the system/high-NA turn the source and optics into a working, high-resolution, high-throughput patterning machine. MASK / PELLICLE PATENTS: the PATTERN CARRIER — defect-free REFLECTIVE EUV MASKS (the mask is also reflective (multilayer + absorber pattern), and must be DEFECT-FREE since defects print onto every chip), the PELLICLE (a thin MEMBRANE stretched over the mask to keep particles off the pattern — but it must SURVIVE the intense EUV power, TRANSMIT EUV with minimal loss, and not degrade — a notoriously HARD materials problem, long a barrier), MASK MATERIALS/BLANKS, and INSPECTION (finding tiny mask defects); mask/pellicle methods are core, high-value, DISTINCTIVE IP (defect-free EUV MASKS and especially the PELLICLE (surviving EUV power while transmitting it — a hard, long-standing materials problem) are core, contested, defensible IP, since mask defects ruin chips and a durable, transparent pellicle is a notoriously difficult enabler). RESIST / PROCESS PATENTS: the IMAGING MATERIAL — EUV PHOTORESIST (the light-sensitive material recording the pattern — needing RESOLUTION, SENSITIVITY (low dose = high throughput), low LINE-EDGE-ROUGHNESS, and low DEFECTS — including new METAL-OXIDE/inorganic resists for better performance), STOCHASTIC EFFECTS (at tiny scales, the random statistics of photons and resist molecules cause variability/defects — a fundamental, key limit at the leading edge), and PROCESS INTEGRATION; resist/process methods are core, high-value, DISTINCTIVE IP (EUV PHOTORESIST (especially metal-oxide/new resists) and managing STOCHASTIC effects (the fundamental random-variation limit) are core, contested, defensible IP, since the resist sets resolution/throughput/defects and stochastics is the leading-edge limit). SYSTEM / HIGH-NA PATENTS: the MACHINE and FUTURE — the SCANNER system (integrating source, optics, mask, wafer stage), OVERLAY/THROUGHPUT, HIGH-NA EUV (the next generation — higher Numerical Aperture optics for even smaller features, with new anamorphic optics/masks — the future of leading-edge patterning), and METROLOGY; system/high-NA methods are high-value IP (the integrated scanner, throughput/overlay, and especially HIGH-NA EUV (the next-gen for smaller nodes) are key value, since the system and the high-NA roadmap define leading-edge patterning's future). EUV-PELLICLE PATENTS: durable transparent EUV pellicles; EUV-pellicle methods are high-value IP (the pellicle is a notoriously hard, long-standing EUV materials problem — a key enabler). Mask/pellicle, resist/process, system/high-NA, and EUV-pellicle are the highest-value IP because the defect-free mask/pellicle, the resist (stochastics), and the system/high-NA roadmap turn EUV into a working, high-resolution, future-proof patterning machine.

EUV lithography startup IP strategy must navigate the asml-zeiss-cymer-monopoly-and-extreme-FTO (EUV scanners are made SOLELY by ASML (with ZEISS optics and CYMER/ASML sources), backed by one of the deepest, most strategic patent estates in technology — so a startup CANNOT build a competing scanner and faces EXTREME FTO — so the realistic opportunity is in the EUV ECOSYSTEM/SUPPLY CHAIN (resists, pellicles, masks, metrology, components, materials) that supply the EUV process, NOT the scanner itself), the resist-and-pellicle-and-mask-materials-are-the-open-opportunities (the EUV ECOSYSTEM has real opportunities in MATERIALS and COMPONENTS that even ASML doesn't make — especially PHOTORESIST (metal-oxide/new EUV resists — a hot, IP-rich area), the PELLICLE (a notoriously hard, long-standing materials problem — durable, transparent, EUV-surviving membranes), MASK blanks/defect-free masks, and METROLOGY/inspection — so a startup's best IP opportunities are in these supply-chain materials/components), the §101-resilient-hardware-and-materials-are-the-strength (EUV IP is semiconductor-equipment/optics/materials/physics IP — strongly §101-RESILIENT — so source, optics, mask, pellicle, and resist claims are strong (a key advantage)), the stochastics-is-the-fundamental-leading-edge-limit (STOCHASTIC effects (random photon/molecule variation causing defects at tiny scales) are a FUNDAMENTAL limit at the leading edge — so resist/process IP that reduces stochastic defects is high-value, since stochastics is the key barrier to smaller, cleaner patterns), the pellicle-is-a-notoriously-hard-long-standing-problem (the PELLICLE (protecting the mask while surviving EUV power and transmitting it) has been a HARD, long-standing barrier — so a durable, high-transmission EUV pellicle is a high-value, defensible materials opportunity), the high-NA-is-the-next-frontier-and-opportunity (HIGH-NA EUV (the next generation for smaller nodes, with new anamorphic optics/masks/resists) is the next frontier — so high-NA-related materials/components/metrology IP is high-upside, as the ecosystem adapts to high-NA), the metrology-and-inspection-are-essential-and-open (METROLOGY and defect INSPECTION (finding tiny defects in masks/wafers, measuring overlay) are essential and somewhat more open — so metrology/inspection IP is a real opportunity), the supply-chain-and-ASML-relationship-strategy (a startup in the EUV ecosystem supplies into ASML's/foundries' processes — so relationships with ASML, foundries (TSMC, Intel, Samsung), and material/equipment majors are strategic, and the path is often to supply/partner), the capital-intensity-and-deep-tech-be-realistic (EUV is the pinnacle of deep-tech/capital-intensity — so be very realistic: a startup plays in a specific material/component/metrology niche, with deep physics/materials expertise, not the scanner), the incumbent-and-FTO (beyond ASML/Zeiss/Cymer, the ecosystem has resist makers (JSR, TOK, Inpria/JSR for metal-oxide), pellicle/mask suppliers, and metrology (KLA) with deep IP — so a startup needs a genuinely novel resist/pellicle/mask/metrology edge, and FTO is significant), the demonstrated-performance-and-fab-qualification-decide (EUV materials/components must be QUALIFIED in real fabs (resolution, defects, throughput, durability) — so demonstrated, fab-qualified performance is decisive, far more than patents), and a landscape where light source, optics, mask/pellicle, resist, and system are the durable assets; understand that (given ASML's monopoly) the opportunity is in resist, pellicle, mask, metrology, and high-NA materials/components, so the durable startup IP is in resist/process, mask/pellicle, metrology, and high-NA-related materials/components — with new EUV resists, durable pellicles, defect-free masks, and metrology often the real moat, and that §101-resilient materials IP, fab qualification, and FTO matter as much as patents; identify whitespace in resists, pellicles, mask materials, metrology, and high-NA materials. EUV LITHOGRAPHY STARTUP IP STRATEGY: RESIST/PROCESS, MASK/PELLICLE, METROLOGY, AND HIGH-NA-RELATED MATERIALS/COMPONENTS ARE THE IP: patent EUV resists, pellicles, masks, and metrology — semiconductor-materials/equipment/optics claims (strongly §101-resilient); ASML-ZEISS-CYMER-MONOPOLY-AND-EXTREME-FTO: EUV scanners made SOLELY by ASML (Zeiss optics/Cymer-ASML sources) with one of the deepest most strategic patent estates — a startup CANNOT build a competing scanner + faces EXTREME FTO — the realistic opportunity in the EUV ECOSYSTEM/SUPPLY CHAIN (resists/pellicles/masks/metrology/components/materials) NOT the scanner; RESIST-AND-PELLICLE-AND-MASK-MATERIALS-ARE-THE-OPEN-OPPORTUNITIES: the EUV ECOSYSTEM has real opportunities in MATERIALS/COMPONENTS even ASML doesn't make — esp. PHOTORESIST (metal-oxide/new resists — hot/IP-rich)/the PELLICLE (a notoriously hard long-standing problem)/MASK blanks-defect-free masks/METROLOGY-inspection — a startup's best IP opportunities; §101-RESILIENT-HARDWARE-AND-MATERIALS-ARE-THE-STRENGTH: semiconductor-equipment/optics/materials/physics IP — strongly §101-RESILIENT (source/optics/mask/pellicle/resist claims strong — a key advantage); STOCHASTICS-IS-THE-FUNDAMENTAL-LEADING-EDGE-LIMIT: STOCHASTIC effects (random photon/molecule variation → defects at tiny scales) a FUNDAMENTAL leading-edge limit — resist/process IP reducing stochastic defects high-value (the key barrier to smaller cleaner patterns); PELLICLE-IS-A-NOTORIOUSLY-HARD-LONG-STANDING-PROBLEM: the PELLICLE (protect the mask + survive EUV power + transmit it) a HARD long-standing barrier — a durable high-transmission EUV pellicle a high-value defensible materials opportunity; HIGH-NA-IS-THE-NEXT-FRONTIER-AND-OPPORTUNITY: HIGH-NA EUV (next-gen — anamorphic optics/masks/resists) the next frontier — high-NA-related materials/components/metrology IP high-upside (the ecosystem adapting to high-NA); METROLOGY-AND-INSPECTION-ARE-ESSENTIAL-AND-OPEN: METROLOGY + defect INSPECTION (find tiny mask/wafer defects/measure overlay) essential + somewhat more open — metrology/inspection IP a real opportunity; SUPPLY-CHAIN-AND-ASML-RELATIONSHIP-STRATEGY: a startup supplies into ASML's/foundries' processes — relationships with ASML/foundries (TSMC/Intel/Samsung)/material-equipment majors strategic (the path often to supply/partner); CAPITAL-INTENSITY-AND-DEEP-TECH-BE-REALISTIC: EUV the pinnacle of deep-tech/capital-intensity — be very realistic: play in a specific material/component/metrology niche with deep physics/materials expertise (not the scanner); INCUMBENT-AND-FTO: beyond ASML/Zeiss/Cymer — resist makers (JSR/TOK/Inpria-JSR metal-oxide)/pellicle-mask suppliers/metrology (KLA) with deep IP — need a genuinely novel resist/pellicle/mask/metrology edge + FTO significant; DEMONSTRATED-PERFORMANCE-AND-FAB-QUALIFICATION-DECIDE: EUV materials/components must be QUALIFIED in real fabs (resolution/defects/throughput/durability) — demonstrated fab-qualified performance decisive (far more than patents); §101-RESILIENT-MATERIALS/FAB-QUALIFICATION/FTO MATTER AS MUCH AS PATENTS: §101-resilient materials IP, fab qualification, and FTO drive value; WHEN TO PATENT: NOVEL RESIST/PELLICLE/MASK/METROLOGY/HIGH-NA METHOD WITH DATA: file once a method shows data (resolution/sensitivity/stochastic-defects-resist + pellicle transmission/durability + mask defectivity + metrology) — semiconductor-materials/equipment/optics claims; demonstrated resist resolution/sensitivity/stochastic defects, pellicle transmission/durability, and mask/metrology performance are the critical EUV IP metrics (with fab qualification decisive); KEY FTO CHECKLIST: ASML/Zeiss/Cymer + resist makers (JSR/TOK/Inpria)/pellicle-mask suppliers/metrology (KLA) + semiconductor-materials companies; light-source (LASER-PRODUCED TIN PLASMA-molten-tin-droplets-CO2-laser/source POWER-THROUGHPUT-the-historical-bottleneck/droplet generation/collector/debris-conversion-efficiency — §101-resilient); optics/mirror (REFLECTIVE OPTICS-everything-absorbs-EUV/MULTILAYER MIRRORS-Mo-Si-reflect-13.5nm/defect-free-figure-precision/reflectivity — §101-resilient, Zeiss); tin-plasma-source; multilayer-mirror; mask/pellicle (defect-free REFLECTIVE EUV MASKS/PELLICLE-membrane-survive-EUV-power-transmit-hard-materials-problem/mask blanks/inspection — the open opportunities); resist/process (EUV PHOTORESIST-resolution-sensitivity-line-edge-roughness-low-defects-METAL-OXIDE-new/STOCHASTIC effects-the-fundamental-limit/process integration — hot/IP-rich); system/high-NA (SCANNER system/overlay-throughput/HIGH-NA EUV-next-gen-anamorphic-optics-masks/metrology); EUV-pellicle (durable transparent — a key enabler); ASML/Zeiss/Cymer monopoly + extreme FTO (supply chain not the scanner); resist + pellicle + mask materials the open opportunities; §101-resilient hardware + materials the strength; stochastics the fundamental leading-edge limit; pellicle a notoriously hard long-standing problem; high-NA the next frontier + opportunity; metrology + inspection essential + open.