Silicon Carbide Device Patents

Silicon carbide device patents cover crystal/wafer innovations; device-structure innovations; gate-oxide/reliability innovations; and fabrication/process and module/application innovations — with IP held by power-semiconductor companies and EV/power firms (in a field of SiC power devices). WHY SILICON CARBIDE DEVICES: they are power semiconductor devices made from SILICON CARBIDE (SiC) — a 'WIDE-BANDGAP' material that vastly OUTPERFORMS ordinary silicon for high-voltage, high-power, high-temperature, high-frequency POWER electronics; SiC can handle far HIGHER voltages and temperatures, SWITCH FASTER, and LOSE LESS energy than silicon, so SiC power devices (especially SiC MOSFETs and diodes) make power conversion SMALLER, LIGHTER, COOLER, and more EFFICIENT; the KILLER application driving the SiC boom is ELECTRIC VEHICLES: SiC inverters EXTEND EV RANGE (less energy lost) and enable FASTER CHARGING — Tesla and others adopted SiC, triggering massive demand; SiC also serves solar inverters, EV chargers, grid, and industrial drives; the CHALLENGES are unique to this hard, difficult material: growing high-quality SiC CRYSTAL/WAFERS is SLOW and DEFECT-prone (SiC is extremely hard, grown at very high temperature, and DEFECTS kill device YIELD — wafer quality and cost are the central bottleneck), the DEVICE STRUCTURE (MOSFET designs — planar vs TRENCH — maximizing performance), the GATE OXIDE/RELIABILITY (the SiC-oxide interface is problematic, historically limiting reliability — a key hard problem), FABRICATION (SiC needs special high-temperature processing), and modules/applications; the industry is also racing to LARGER (200mm) wafers to cut cost. MAJOR PLAYERS: WOLFSPEED, INFINEON, STMICROELECTRONICS, ONSEMI, ROHM, plus EV and power companies. Crystal/wafer, device structure, gate oxide/reliability, fabrication/process, and module/application are the core SiC-device patent domains — and wafers, devices, gate oxide, fabrication, and modules are the open whitespace.

Crystal/wafer innovations; device-structure innovations; defect-reduction innovations; and trench-gate innovations represent core SiC-device patent domains — and the SiC wafer (the central bottleneck) and the device structure are the foundational, high-value capabilities. CRYSTAL / WAFER PATENTS: the SiC SUBSTRATE and epitaxy — bulk SiC CRYSTAL GROWTH (slow, high-temperature sublimation/PVT growth, and newer methods), DEFECT REDUCTION (MICROPIPES, dislocations, stacking faults that kill device yield), EPITAXIAL layer growth (the active device layer), and the move to LARGER (150mm→200mm) wafers; crystal/wafer methods are core, high-value, DISTINCTIVE IP (the SiC WAFER is the FOUNDATIONAL material and the CENTRAL cost/yield BOTTLENECK — SiC is hard to grow defect-free, and wafer cost/quality/size dominate SiC device economics, so crystal growth, defect reduction, and larger-wafer technology are the deepest, most strategically-critical, contested areas, and wafer supply is itself a major industry constraint). DEVICE-STRUCTURE PATENTS: the SiC power DEVICE — SiC MOSFETs (PLANAR vs TRENCH GATE — trench packs more performance but is harder to make reliably), Schottky/JBS DIODES, and structures maximizing on-RESISTANCE (lower loss), BREAKDOWN voltage, and SWITCHING performance; device-structure methods are core, high-value, distinctive IP (the device structure — especially TRENCH-gate MOSFETs that improve performance, and optimizing the on-resistance/breakdown/switching tradeoffs — is a key, contested, defensible area). DEFECT-REDUCTION PATENTS: reducing crystal defects that kill yield; defect-reduction methods are high-value IP (defect reduction directly improves yield and cost — the central SiC economics lever). TRENCH-GATE PATENTS: trench-gate MOSFET structures and their reliable fabrication; trench-gate methods are high-value IP (trench gates improve performance but are a key, hard design area). Crystal/wafer, device-structure, defect-reduction, and trench-gate are the highest-value core IP because the SiC wafer and device structure are exactly what determine SiC's performance, yield, and cost.

Gate-oxide/reliability innovations; fabrication/process innovations; module/application innovations; and interface innovations represent additional SiC-device patent domains — and the gate oxide (a key hard problem), SiC-specific processing, and modules/applications are where reliability, manufacturability, and value lie. GATE-OXIDE / RELIABILITY PATENTS: the gate OXIDE and its INTERFACE with SiC — improving the problematic SiC-SiO2 INTERFACE (interface TRAPS that hurt electron MOBILITY and reliability), gate-oxide RELIABILITY (the oxide must survive high fields/temperatures for years), and THRESHOLD-voltage stability; gate-oxide/reliability methods are core, high-value, DISTINCTIVE IP (the SiC-oxide INTERFACE is a NOTORIOUS, historically-LIMITING problem — interface traps reduce performance and the gate oxide's long-term reliability has been a key concern — so improving the interface (nitridation, passivation) and gate-oxide reliability is a critical, contested, defensible area essential to making SiC MOSFETs trustworthy for EVs). FABRICATION / PROCESS PATENTS: manufacturing SiC devices — high-temperature ION IMPLANTATION and ANNEALING (SiC needs very high temperatures silicon doesn't), EDGE TERMINATION (handling high voltage at device edges), CONTACTS (ohmic contacts to SiC), and SiC-specific process steps; fabrication/process methods are core, high-value IP (SiC requires processing that ordinary silicon doesn't (extreme-temperature implant/anneal, edge termination, contacts), so SiC-specific fabrication is a key, defensible area, and process maturity drives yield/cost). MODULE / APPLICATION PATENTS: packaging and applications — SiC power MODULES (packaging SiC for high performance — overlaps power-semiconductor packaging), EV INVERTERS (the killer app — maximizing range/efficiency), CHARGERS, SOLAR inverters, and grid — plus gate drive and system integration; module/application methods are high-value IP (SiC's value is realized in MODULES and applications, especially EV INVERTERS (the dominant driver), and module/packaging that exploits SiC's high-frequency/high-temperature capability and gate-drive integration are key value areas, overlapping power-semiconductor packaging). INTERFACE PATENTS: SiC-SiO2 interface engineering (nitridation/passivation) for mobility/reliability; interface methods are high-value IP (the interface is the key reliability/performance lever). Gate-oxide/reliability, fabrication/process, module/application, and interface are the highest-value application IP because the gate oxide, SiC-specific processing, and modules/applications are exactly what make SiC devices reliable, manufacturable, and valuable.

Silicon carbide device startup IP strategy must navigate the wafer-is-the-central-bottleneck-and-IP reality (the SiC WAFER (crystal growth, defect reduction, larger 200mm wafers) is the FOUNDATIONAL material, the central cost/yield BOTTLENECK, and a strategic supply constraint — wafer technology and supply are where much of the value and contention sit, so crystal/wafer IP (or securing wafer supply) is critical), the EV-is-the-killer-app tailwind (ELECTRIC VEHICLES are the dominant demand driver (SiC inverters extend range and enable fast charging — Tesla-led adoption triggered massive demand) — the EV market is the central opportunity, alongside solar/chargers/grid), the capital-intensive/foundry-coupled reality (SiC is extremely CAPITAL-INTENSIVE (fabs, crystal growth) and dominated by vertically-integrated IDMs (Wolfspeed, Infineon, ST, onsemi, ROHM) — a startup competing on complete devices needs enormous capital, so many play in specific IP (device structures, gate oxide, wafer tech), license, or supply materials/equipment), the gate-oxide-reliability-is-the-hard-problem insight (the SiC-oxide INTERFACE and gate-oxide reliability are a notorious, historically-limiting problem — improving interface/reliability is a key, defensible, much-needed IP area essential for EV-grade trust), the trench-vs-planar-device fork (TRENCH-gate MOSFETs (higher performance, harder to make) vs planar is a key device-IP battleground), the larger-wafer-cost-race insight (the industry is racing to 200mm wafers to cut cost — larger-wafer/defect-reduction IP is strategically valuable), the materials/equipment-supplier opportunity (a startup can supply SiC wafers, crystal-growth or processing equipment/materials, or device IP rather than competing on finished devices — picks-and-shovels and licensing are viable strategies), the reliability/qualification reality (SiC for EVs needs automotive qualification (AEC-Q) and proven long-term reliability (especially gate oxide) — qualification and reliability data matter as much as patents and are a real barrier), the incumbent-IP-density/FTO reality (SiC has dense IP across wafers/devices/fabrication held by incumbents — careful FTO and a genuine wafer, device, gate-oxide, or process edge are essential), the geopolitics/supply-chain insight (SiC supply chain (wafers, substrates) is strategically important and partly geopolitically contested — supply security matters), and a landscape where wafers, devices, gate oxide, fabrication, and modules are the durable assets; understand that wafers, reliability, and EV demand decide, so the durable startup IP is in wafer/crystal tech, device structures, gate-oxide reliability, and fabrication — with crystal/wafer technology, device structure/gate-oxide reliability, and process/manufacturing often the real moat, and that yield/cost (wafer), reliability, device performance, qualification, and FTO matter as much as patents; identify whitespace in wafer/defect reduction, gate oxide, trench devices, and 200mm. SILICON CARBIDE DEVICE STARTUP IP STRATEGY: WAFER/CRYSTAL TECH, DEVICE STRUCTURES, GATE-OXIDE RELIABILITY, AND FABRICATION ARE THE IP: patent wafer/crystal tech, device structures, gate-oxide reliability, and fabrication; WAFER IS THE CENTRAL BOTTLENECK + IP: crystal growth/defect reduction/200mm wafers are the foundational material + central cost/yield bottleneck + a supply constraint — wafer tech (or securing supply) is critical; EV IS THE KILLER-APP TAILWIND: EVs are the dominant demand driver (SiC inverters extend range/fast charging — Tesla-led) — the central opportunity (+ solar/chargers/grid); CAPITAL-INTENSIVE/FOUNDRY-COUPLED: extremely capital-intensive + IDM-dominated (Wolfspeed/Infineon/ST/onsemi/ROHM) — startups play in specific IP/license/supply materials-equipment vs complete devices; GATE-OXIDE-RELIABILITY IS THE HARD PROBLEM: the SiC-oxide interface + gate-oxide reliability are notorious/historically-limiting — improving interface/reliability is a key defensible much-needed IP (essential for EV trust); TRENCH-VS-PLANAR-DEVICE FORK: trench-gate (higher performance, harder) vs planar — a device-IP battleground; LARGER-WAFER-COST-RACE: racing to 200mm to cut cost — larger-wafer/defect-reduction IP strategically valuable; MATERIALS/EQUIPMENT-SUPPLIER OPPORTUNITY: supply SiC wafers/crystal-growth-processing equipment/device-IP vs finished devices (picks-and-shovels/licensing viable); RELIABILITY/QUALIFICATION: automotive qualification (AEC-Q) + proven reliability (esp. gate oxide) — matter as much as patents (a real barrier); INCUMBENT-IP-DENSITY/FTO: dense IP across wafers/devices/fabrication — careful FTO + a real wafer/device/gate-oxide/process edge; GEOPOLITICS/SUPPLY-CHAIN: strategically important + partly contested — supply security matters; YIELD-COST/RELIABILITY/PERFORMANCE/QUALIFICATION/FTO MATTER AS MUCH AS PATENTS: yield/cost (wafer), reliability, device performance, qualification, and FTO drive value; WHEN TO PATENT: NOVEL WAFER/DEVICE/GATE-OXIDE/FABRICATION METHOD WITH MEASURED PERFORMANCE: file once a method shows measured results (wafer defect density/size/cost + on-resistance/breakdown/switching + gate-oxide reliability/interface + yield) — measured wafer defect/cost, gate-oxide reliability, and device performance are the critical SiC IP metrics; KEY FTO CHECKLIST: Wolfspeed/Infineon/STMicroelectronics/onsemi/ROHM + EV/power companies; crystal/wafer (bulk SiC crystal growth/DEFECT reduction-micropipes-dislocations/epitaxy/150-200mm — the foundational material + central bottleneck); device structure (SiC MOSFETs PLANAR-vs-TRENCH/Schottky-JBS diodes/on-resistance-breakdown-switching); defect-reduction (yield/cost lever); trench-gate (higher performance/reliable fabrication); gate oxide/reliability (SiC-SiO2 INTERFACE traps-mobility/gate-oxide reliability/threshold stability — a notorious hard problem); fabrication/process (high-temperature implant-anneal/edge termination/ohmic contacts — SiC-specific); module/application (SiC power MODULES overlaps power-semiconductor packaging/EV-INVERTERS-killer-app/chargers/solar/grid + gate drive); interface (SiC-SiO2 nitridation-passivation); wafer the central bottleneck; EV the killer app; gate-oxide reliability the hard problem.