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Industry Patents · Semiconductors · CHIPS Act

Semiconductor Patents

Chip IP layers (process, mask work, architecture, SEPs, EDA), the CHIPS Act, patent pools, FRAND licensing, and patent strategy across fabless, IDM, foundry, and IP licensor models.

IP Layers

Six layers of semiconductor IP protection

A single chip can be covered by patents and other IP rights held by multiple different companies simultaneously. Chip companies must navigate all relevant layers.

1Process patents

Cover the manufacturing process used to fabricate semiconductor devices — photolithography steps, doping sequences, deposition techniques (CVD, ALD, PVD), etch processes, and chemical-mechanical planarization (CMP). Process patents are typically owned by IDMs (Intel, Samsung, GlobalFoundries) and foundries (TSMC, SMIC). They protect the how of chip fabrication, not the design itself. Critical for advanced nodes (sub-5nm): fin pitch, EUV lithography step-and-scan parameters, gate-all-around (GAA) nanosheet formation. Process patents often cannot be independently verified without a fab — detection requires reverse-engineering through cross-sectional TEM analysis.

Typical holders

IDMs, foundries

Strength / design-around

Very high — nearly impossible to design around at advanced nodes

2Layout design (mask work) protection

Semiconductor chip layouts in the US are protected under the Semiconductor Chip Protection Act of 1984 (SCPA), 17 U.S.C. §§ 901–914 — not traditional patent law. SCPA protection lasts 10 years and protects the 3D arrangement of layers in an integrated circuit (the 'mask work'). SCPA protection is narrower than patent protection: reverse engineering for purposes of study and teaching is explicitly permitted (§ 906), and registration requires deposit of identifying material at the Copyright Office within 2 years of commercial exploitation. Note: mask work protection does NOT overlap with utility patents — a chip can have both SCPA mask work protection AND utility patents on the architecture or process.

Typical holders

Chip designers — both fabless and IDMs

Strength / design-around

Moderate — reverse engineering for study allowed; 10-year term (shorter than patent)

3Architecture/microarchitecture patents

Cover the design of the processor or chip architecture — instruction set extensions, pipeline organization, cache hierarchy, branch prediction algorithms, out-of-order execution logic, memory management unit (MMU) design, and interconnect fabric (e.g., AMBA, CHI, TileLink). These are the most litigated semiconductor patents because they protect commercially differentiated features. ARM Holdings owns thousands of architecture patents covering designs licensed broadly (Apple, Qualcomm, Samsung, MediaTek all license ARM ISA). RISC-V is an open ISA that eliminates ISA-level patent risk but implementations may still infringe architecture patents on specific microarchitectural features.

Typical holders

ARM, Intel, IBM, AMD, Qualcomm, Apple (largest portfolios by volume)

Strength / design-around

High — architecture patents often cover essential design choices

4Standard-essential patents (SEPs) in chipsets

Wireless chipsets (Wi-Fi, 5G/NR, LTE, Bluetooth, NFC) must implement communications standards set by ETSI, IEEE, and 3GPP. Patents that are essential to implementing these standards are SEPs — they cannot be designed around while remaining standard-compliant. SEP holders who declared their patents to a standards body (ETSI/IEEE) must license SEPs on FRAND (Fair, Reasonable, and Non-Discriminatory) terms. Qualcomm, Nokia, Ericsson, InterDigital, Huawei, and Samsung hold large 5G/LTE SEP portfolios. Chipset manufacturers (Apple, MediaTek, Samsung Exynos) must navigate SEP licensing as a mandatory cost of making standards-compliant chips. The FTC sued Qualcomm in 2017 for anticompetitive SEP licensing practices (no-license-no-chips policy); the 9th Circuit ruled in Qualcomm's favor in 2020 (FTC v. Qualcomm, 969 F.3d 974 (9th Cir. 2020)).

Typical holders

Qualcomm, Nokia, Ericsson, InterDigital, Huawei, Samsung, LG (declared to ETSI/3GPP/IEEE)

Strength / design-around

Essential by definition — cannot design around; must license on FRAND terms

5EDA tool and design methodology patents

Electronic design automation (EDA) software — used to design, simulate, verify, and place-and-route chips — is itself heavily patented. Companies like Synopsys, Cadence, and Siemens EDA (formerly Mentor Graphics) hold tens of thousands of patents on tools like place-and-route algorithms, logic synthesis, formal verification (model checking), DRC (design rule checking), LVS (layout versus schematic), and physical verification flows. EDA tool patents are a separate IP layer — a chip designer who buys an EDA tool license gets freedom to use the tool but does not receive immunity from patents covering chip architectures the tool might implement. EDA patent disputes between Synopsys and Cadence have been ongoing for decades.

Typical holders

Synopsys, Cadence, Siemens EDA (Mentor Graphics)

Strength / design-around

High within EDA industry; EDA customers face tool patent risk differently from chip patent risk

6Memory and storage patents

DRAM, NAND flash, and NOR flash architectures are among the most heavily patented areas of semiconductors. Key examples: Rambus Inc. controlled DRAM interface patents for decades and collected large royalties from DRAM manufacturers before antitrust rulings limited its practices (Rambus Inc. v. Infineon, FTC v. Rambus). JEDEC (standards body for memory standards — DDR4, DDR5, LPDDR5, HBM3) requires members to disclose patents essential to JEDEC standards and commit to reasonable and non-discriminatory licensing. Samsung, Micron, and SK Hynix hold most manufacturing-level memory patents. Emerging memory technologies (3D NAND, ReRAM, MRAM, PCM, HBM) are intensely contested areas.

Typical holders

Samsung, Micron, SK Hynix, Kioxia, Western Digital; historically Rambus for DRAM interfaces

Strength / design-around

Very high — memory architecture and manufacturing patents are foundational to entire device categories

Policy

CHIPS and Science Act (2022) — What It Means for Patent Strategy

What the CHIPS Act does

The CHIPS and Science Act (Pub. L. 117-167, signed August 9, 2022) provides $52.7 billion in federal funding for domestic semiconductor manufacturing and research. Key provisions: $39 billion in manufacturing incentive grants (CHIPS for America Fund); 25% Advanced Manufacturing Investment Tax Credit (AMITC) under § 48D of the Internal Revenue Code for qualifying semiconductor manufacturing investments; $11 billion for R&D including NSTC (National Semiconductor Technology Center) and NAPMP (National Advanced Packaging Manufacturing Program); $2 billion for the CHIPS Defense Fund for DoD-specific semiconductor needs.

National security and foreign ownership restrictions

CHIPS Act recipients must agree to 'guardrails' — restrictions on expansion of semiconductor manufacturing in 'countries of concern' (primarily China) for 10 years after receiving CHIPS funding. Recipients also cannot enter into joint research or technology licensing agreements with foreign entities of concern if it would pose a national security risk. These restrictions create significant constraints on IP licensing strategy for CHIPS Act recipients: they may be unable to license their manufacturing IP to Chinese foundries, design firms, or research institutions for the duration of the funding restrictions.

IP and patent implications for CHIPS recipients

CHIPS Act R&D grants (unlike manufacturing grants) come with march-in rights provisions modeled on the Bayh-Dole Act (35 U.S.C. §§ 200–212). For federally funded semiconductor R&D, the US government retains a non-exclusive, royalty-free license to practice the invention (28 U.S.C. § 1498). The contractor (recipient) retains ownership and can commercialize, but if the recipient fails to achieve practical application, the government can 'march in' and license the invention to third parties. March-in rights for CHIPS R&D remain untested as of 2024 but are a real constraint on patent licensing strategy for NSTC participants.

Advanced Manufacturing Investment Tax Credit (AMITC) — § 48D

The 25% AMITC under IRC § 48D applies to 'qualified property' used in the manufacturing of semiconductors or semiconductor manufacturing equipment. The credit applies to investment in semiconductor manufacturing facilities, not to R&D expenses (which are addressed separately under IRC § 41 R&D credit). Important: the § 48D AMITC is entirely separate from patent strategy — receiving the credit does not affect patent ownership, licensing rights, or prosecution. However, CHIPS Act recipients subject to the guardrails cannot use government-subsidized facilities in licensed joint ventures with foreign entities of concern.

Business Models

Patent strategy by business model

Fabless (design only)

Qualcomm, NVIDIA, AMD, Apple (custom silicon), MediaTek, Marvell, Arm

Patent strategy focuses on architecture patents, algorithm patents, and SEPs. No process patents (no fab). Key risks: (1) foundry may be unable to manufacture designs without infringing third-party process patents; (2) fabless companies rely entirely on foundry IP for manufacturing — contractual indemnification from foundry (TSMC, Samsung Foundry) is critical; (3) fabless startups must budget for freedom-to-operate analysis before tapeout since post-tapeout design changes are extremely expensive. ARM-based designs must negotiate separate license for ARM ISA and physical IP (standard cells, IO libraries) — these are IP licenses on top of foundry process.

IDM (Integrated Device Manufacturer)

Intel, Samsung Semiconductor, Texas Instruments, Microchip Technology

IDMs hold both process patents (manufacturing) and architecture patents. Largest overall portfolio sizes. Intel's patent portfolio (~100,000 patents) spans manufacturing processes, chip architectures, packaging technology (EMIB, Foveros), and platform IP. IDMs are more insulated from foundry risk (they have their own fabs) but must manage FTO for designs that will be manufactured in external foundries (Intel Foundry Services licensing in third-party designs raises complex IP questions). Cross-licensing between IDMs (Intel-AMD cross-license, Intel-Samsung agreements) is standard practice to reduce mutual litigation risk.

Foundry (manufacturing only)

TSMC, GlobalFoundries, SMIC, UMC, Samsung Foundry

Foundries hold extensive process patents and provide customers with process design kits (PDKs) under license. The foundry-customer relationship includes IP provisions: (1) customer designs remain customer IP; (2) foundry process IP stays with foundry; (3) foundry typically provides limited indemnification for process-related infringement but NOT for customer architecture/design infringement. TSMC's advanced node leadership (3nm, 2nm) is partly protected by thousands of process patents. TSMC actively litigates process IP — filed suit against GlobalFoundries in 2019 over 25 process and design patents.

IP licensing (fabless, fabs-nothing)

ARM Holdings (now SoftBank-owned), Rambus, MPEG LA, InterDigital

Pure IP licensing companies — no products, no fab. Patent portfolio is the only business. ARM's licensing model: (1) Architecture License (right to design custom ARM-ISA-compatible cores — Apple M-series, Qualcomm Oryon are architecture license products); (2) Processor License (right to implement a specific ARM-designed core — Cortex-A78 implementation by MediaTek); (3) Physical IP License (standard cells, IO libraries optimized for a specific foundry node). ARM licenses represent a unique IP risk for fabless chip companies: ARM is currently transitioning from fixed-fee licensing to royalty-on-ACV (aggregate contract value) pricing — the change is contested by Qualcomm and others and is subject to ongoing arbitration (Arm v. Qualcomm, Delaware).

SEPs & Patent Pools

Standard-essential patents and licensing frameworks

Via Licensing (now part of Avanci)LTE, 5G NR, 802.11 Wi-Fi

Via Licensing was one of the original patent pool administrators for wireless standards. Merged with Avanci in 2022. Avanci now administers pools for 2G/3G/4G/5G cellular patents, licensing to IoT device manufacturers and automakers (Vehicle 5G Connectivity) at fixed per-unit rates. Avanci's automotive licensing model (fixed royalty per connected vehicle regardless of number of cellular SEPs used) has been controversial but adopted by most major automakers.

JEDEC IP PolicyDDR4, DDR5, LPDDR5, HBM3, GDDR6 memory standards

JEDEC (Joint Electron Device Engineering Council) requires member companies to disclose patents they know to be essential to JEDEC standards and to commit to licensing those patents on RAND (Reasonable and Non-Discriminatory) terms. JEDEC does not operate a formal patent pool — each member licenses its SEPs individually. The Rambus disputes (in which Rambus participated in JEDEC while allegedly concealing SEPs, then withdrew and asserted them) led to major FTC enforcement action and shaped JEDEC's current disclosure requirements.

IEEE-SA Patent Policy802.11 Wi-Fi (all variants), 802.3 Ethernet, 802.15 Bluetooth

The IEEE Standards Association (IEEE-SA) patent policy requires that for essential patents declared to IEEE, the SEP holder commit to one of three levels of licensing obligation: (LOA Option 1) reasonable rates, terms, and conditions (RAND); (LOA Option 2) not to enforce essential patent claims; or (LOA Option 3) reciprocal licensing. The 2015 IEEE-SA policy update to define 'reasonable rates' by excluding the value of the standard itself from the royalty calculation was controversial — Qualcomm and InterDigital objected; Ericsson and Nokia adopted the updated policy. Wi-Fi chipset manufacturers (Broadcom, Qualcomm Atheros, Intel, MediaTek) must navigate IEEE-SA SEP licensing from multiple holders.

ETSI/3GPP FRAND FrameworkGSM, WCDMA (3G), LTE (4G), 5G NR

ETSI (European Telecommunications Standards Institute) and 3GPP (3rd Generation Partnership Project) set the cellular standards implemented in all LTE and 5G chips. ETSI's IPR policy requires SEP holders to commit to FRAND licensing before the standard is published (ETSI IPR Policy, Clause 6.1). ETSI does not define FRAND rates — that is left to negotiation and court determination. The battle over FRAND rate-setting methodology for 5G SEPs has been litigated globally: UK (Unwired Planet v. Huawei [2020] UKSC 37 — UK courts can set global FRAND rates), EU (Huawei v. ZTE C-170/13 [2015] — framework for FRAND injunctions), US (FTC v. Qualcomm). FRAND licensing costs are a significant, non-optional line item in chipset gross margin.

Case Law

Key semiconductor patent cases

FTC v. Qualcomm, 969 F.3d 974 (9th Cir. 2020)

Reversed district court ruling that Qualcomm's 'no-license-no-chips' policy and exclusive dealing with Apple violated antitrust law. The 9th Circuit held that Qualcomm's refusal to license SEPs to chip rivals does not violate the Sherman Act's duty to deal doctrine, and that FRAND commitments create contract obligations enforceable by implementers, not antitrust duties enforced by the FTC. Significance: preserved Qualcomm's licensing model; significantly shaped global debate on SEP-antitrust intersection.

Arm Ltd. v. Qualcomm Inc. (D. Del., filed 2022)

Arm filed suit against Qualcomm and Nuvia (acquired by Qualcomm in 2021) alleging that Qualcomm's acquisition of Nuvia transferred Nuvia's ARM architecture license rights to Qualcomm in violation of the architecture license agreement, which prohibits transfer. Qualcomm argues its existing ARM architecture license covers the Nuvia-origin designs. Case pending as of 2024. Significance: outcome could fundamentally affect whether fabless companies can acquire IP-heavy startups without triggering license termination.

Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081 (Fed. Cir. 2003)

Federal Circuit upheld most of Rambus's DRAM interface patents against Infineon's inequitable conduct and antitrust defenses. Rambus had participated in JEDEC while prosecuting patents it later asserted against DDR SDRAM. While the FTC later found Rambus violated antitrust law through JEDEC participation (FTC v. Rambus, 2006 — later reversed on appeal), the Federal Circuit in the patent cases upheld many Rambus patent claims. Significance: paradigmatic case for patent ambush in standard-setting; shaped JEDEC and IEEE-SA IPR disclosure requirements.

TSMC v. GlobalFoundries (N.D. Cal. and ITC, 2019)

TSMC filed suit in US District Court (N.D. Cal.) and the ITC (Section 337) alleging GlobalFoundries infringed 25 TSMC process and product patents related to FinFET transistor fabrication, HKMG gate dielectric processes, and multi-patterning lithography. GlobalFoundries countersued. Cases settled in 2020 under an undisclosed agreement that included a patent cross-license between TSMC and GlobalFoundries. Significance: demonstrated that leading-edge foundry process patents are aggressively enforced between direct competitors.

FAQ

Frequently asked questions

What types of patents protect a semiconductor chip?

A single semiconductor chip typically has multiple layers of IP protection from multiple different IP owners. The main categories are: (1) Process patents: cover the manufacturing steps used to fabricate the chip — lithography, doping, deposition, etch. Owned by foundries (TSMC, GlobalFoundries) and IDMs (Intel, Samsung). Cannot be designed around at a given node; (2) Mask work protection under the Semiconductor Chip Protection Act of 1984 (17 U.S.C. §§ 901–914): covers the 3D arrangement of circuit elements in the chip layout. 10-year term. Reverse engineering for study is permitted; (3) Architecture patents: cover the microarchitecture of the processor or chip design — pipeline, cache hierarchy, branch prediction, memory system. These are the most litigated chip patents; (4) Standard-essential patents (SEPs): patents essential to implementing wireless or memory standards (5G/LTE for modem chips; DDR for memory interfaces). Must be licensed on FRAND terms; (5) EDA and design methodology patents: cover tools used to design chips — owned by Synopsys, Cadence, Siemens EDA. EDA tool licenses don't immunize customers from third-party architecture patents. A fabless chip startup must navigate all five layers — particularly process patents (through foundry indemnification), architecture patents (FTO analysis), and SEPs (mandatory FRAND licensing if building standards-compliant wireless chips).

What does the CHIPS Act mean for semiconductor patent strategy?

The CHIPS and Science Act (Pub. L. 117-167, 2022) provides $52.7 billion for domestic semiconductor manufacturing and R&D, but it comes with significant IP-relevant constraints. Manufacturing grants (the $39B fabrication incentive) come with 10-year 'guardrails' prohibiting recipients from expanding semiconductor manufacturing capacity in 'countries of concern' (primarily China) and from certain technology licensing with foreign entities of concern. This directly limits the IP licensing strategy of CHIPS grant recipients — they may be unable to license process technology to Chinese foundries or joint-venture partners for a decade. R&D grants (NSTC, NAPMP, university programs) come with Bayh-Dole-style provisions: recipients own the resulting patents but the US government receives a royalty-free license and retains march-in rights if the invention is not commercialized. CHIPS Act recipients should structure their R&D efforts carefully — work funded by CHIPS R&D grants will be subject to these government license and march-in provisions. The 25% Advanced Manufacturing Investment Tax Credit (§ 48D AMITC) is tax-side and does not directly affect patent ownership, but CHIPS funding guardrails and the tax credit eligibility rules together constrain where subsidized manufacturing capacity can be deployed and licensed.

What is FRAND licensing and how does it affect chip companies?

FRAND stands for Fair, Reasonable, and Non-Discriminatory — the licensing commitment that holders of standard-essential patents (SEPs) must make when their patents are declared essential to a telecommunications or technology standard. For semiconductor companies, FRAND licensing matters most for wireless chipsets (5G/LTE modems, Wi-Fi chips, Bluetooth) and memory interfaces. Here's how it works: (1) A standards body (ETSI for cellular, IEEE-SA for Wi-Fi/Ethernet) develops a standard (5G NR, 802.11ax). Participating companies declare patents they believe are essential to implementing the standard; (2) In exchange for the standard adopting their technology, declared SEP holders commit to license those SEPs on FRAND terms to any implementer who requests a license; (3) An implementer who needs to build a 5G modem chip CANNOT design around SEPs — by definition, implementing the standard requires practicing the SEPs. They must negotiate a FRAND license; (4) If FRAND rates can't be agreed upon, courts can determine them (UK Unwired Planet v. Huawei; US courts; EU member state courts). Courts have increasingly been willing to set global FRAND royalty rates. For a fabless company building 5G chipsets, FRAND licensing is a mandatory cost of goods — not optional. Major 5G SEP holders (Qualcomm, Nokia, Ericsson, Huawei, Samsung, InterDigital) actively license chipset manufacturers, often at per-unit royalty rates. The chipset manufacturer must model FRAND licensing costs as a non-negotiable line item in chip gross margin before committing to a wireless standard-compliant product.

How do ARM license agreements work and what are the risks?

ARM Holdings (now owned by SoftBank and publicly traded as ARM) licenses its intellectual property — primarily processor architecture and physical IP — to almost every major chip company in the world. There are three main ARM license types: (1) Architecture License (ALA): authorizes the licensee to design custom processor cores that implement the ARM instruction set architecture (ISA). Holders of ALAs include Apple (M-series, A-series), Qualcomm (Oryon/Snapdragon X Elite), and Amazon (Graviton). ALAs give maximum design freedom — the licensee can create entirely custom microarchitectures that are ISA-compatible. ALAs have historically been fixed-fee with per-unit royalties, but ARM is transitioning ALA pricing to include royalties based on the chip's selling price or ACV, creating significant cost uncertainty for ALA holders; (2) Processor License (PLA): authorizes the licensee to implement a specific ARM-designed processor core (e.g., Cortex-A78, Cortex-X4) in a product. The licensee does not design the core — they take ARM's RTL (register-transfer level) implementation and integrate it. PLA royalties are per-chip; (3) Physical IP License: access to ARM's optimized standard cell libraries, IO pads, and other physical components — tied to specific foundry process nodes. Risks for chip companies: (a) License transferability — ARM licenses are generally non-transferable; acquiring a company with an ARM license (e.g., Qualcomm's acquisition of Nuvia) may not automatically transfer the license, as the Arm v. Qualcomm litigation (D. Del., filed 2022) illustrates; (b) Royalty escalation — ARM is actively pushing for royalty increases that could significantly raise chip COGS for existing licensees; (c) RISC-V as an alternative — the open ISA RISC-V eliminates ARM ISA-level licensing risk (no patent license needed for the ISA) but implementations may still face architecture patent risk on specific microarchitectural choices.

Can a fabless chip startup build a patent portfolio and why does it matter?

Yes — and for most well-funded fabless startups, building a patent portfolio is strategically important even if the startup has no current plans to litigate. Here's why: (1) Defensive cross-licensing: the semiconductor industry is a dense patent thicket. When a large chip company alleges infringement (or sends a licensing demand), having a portfolio of your own patents gives you chips to negotiate with. Most major chip company disputes are resolved through cross-licenses — 'you license my patents, I license yours, we both walk away.' Without your own portfolio, you have nothing to trade; (2) Fundraising and acquisition signaling: patent portfolios are tangible IP assets that appear on the balance sheet (if capitalized) or are disclosed in due diligence. VCs and acquirers use patent counts as a proxy (imperfect, but real) for technical differentiation and defensibility. Chip startups have been acquired primarily for their patent portfolios even when the product didn't succeed; (3) ITC § 337 exclusion orders: if a competitor imports infringing chips into the US, a patent portfolio enables an ITC Section 337 complaint — which can result in an import exclusion order faster than district court injunctions; (4) Freedom to operate: the process of building a portfolio (prior art searches, claim drafting) naturally surfaces third-party patents that the startup's chip might infringe — identifying FTO risks before tapeout is dramatically cheaper than post-tapeout design changes. For the portfolio strategy: focus first on the architecture and algorithm inventions that are core to the chip's differentiated performance — these are the claims most likely to have licensing value. Process patents are not available to fabless companies. SEPs require participating in standards bodies. The most valuable fabless portfolio consists of architecture patents covering what makes your chip faster, more efficient, or more capable than competitors.

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