Semiconductor Patent Strategy

The semiconductor industry relies on multiple overlapping patent categories: CIRCUIT DESIGN PATENTS: patents on circuit architectures; specific cell designs; novel logic structures; memory cell designs (DRAM; NAND Flash; SRAM); processor microarchitecture; digital signal processing circuits; analog circuit topologies (PLLs; ADCs; DACs); SCOPE: generally claim the functional structure (circuit elements + their interconnections); typically covers the design itself; FABRICATION PROCESS PATENTS: patents on the manufacturing process; the most valuable secrets in the industry; gate dielectric materials (high-k dielectrics for CMOS scaling); transistor structures (FinFET; GAAFET); photolithography methods (EUV lithography process optimization); deposition techniques (ALD; CVD; MOCVD); etching processes (atomic layer etching); chemical mechanical planarization; SCOPE: cover the sequence of process steps; specific temperatures, pressures, and chemistries; equipment configurations; these patents often expire before the process is fully deployed at scale; LAYOUT PATTERNS: specific physical layout configurations; memory array layouts; standard cell libraries; these may be protected by patents AND by the Semiconductor Chip Protection Act (SCPA) mask work registration; PACKAGING AND INTERCONNECT: advanced packaging patents (3D stacking; chiplet architectures; through-silicon vias (TSVs); HBM memory configurations); interposer designs; bump architectures; gaining importance as Moore's law slows; STANDARDS-ESSENTIAL PATENTS (SEPs): patents covering wireless standards (Wi-Fi; 4G LTE; 5G NR; Bluetooth; USB; PCIe; Ethernet); extremely valuable because they are essential to implementing the standard; subject to FRAND licensing commitments; key holders: Qualcomm; Ericsson; Nokia; InterDigital; Apple; Samsung; Huawei; EDA/DESIGN TOOL PATENTS: patents on electronic design automation tools; simulation methods; formal verification techniques; synthesis algorithms.

Cross-licensing is the dominant patent strategy among major semiconductor companies: WHAT CROSS-LICENSING IS: two or more companies agree to license each other's patents, typically under a blanket agreement covering all patents owned by each party at the time; each party can practice the other's patents without paying per-patent royalties or risking infringement suits; ECONOMIC RATIONALE: in semiconductors, every major company needs access to thousands of patents owned by competitors; litigation over all relevant patents would be prohibitively expensive and would threaten the entire industry's ability to function; cross-licensing converts patent litigation risk into a negotiated business arrangement; NET BALANCING PAYMENT: if one party's portfolio is more valuable than the other's, a net balancing payment (cash or royalty) is agreed; the party with the weaker portfolio pays the stronger; IBM'S CROSS-LICENSING PROGRAM: IBM has one of the largest semiconductor patent portfolios; IBM cross-licenses with virtually every major semiconductor company; IBM received over $1 billion/year in patent licensing revenue in the 1990s-2000s; QUALCOMM'S CDMA/WCDMA/LTE LICENSING MODEL: Qualcomm licenses its SEPs and baseband chip patents separately from cross-licensing; charges royalties on the entire device price (controversial; FTC and foreign antitrust regulators challenged); CHIPS ACT IMPLICATIONS: as chip supply chains become strategic, governments are increasingly interested in how patent licensing affects chip availability and cost; ARM's LICENSING MODEL: ARM licenses its processor architecture IP (instruction set + microarchitecture) to chip designers; foundational to the mobile and IoT chip ecosystem; fabless companies pay per-unit royalties or upfront license fees; NEWCOMER PROBLEM: companies without large patent portfolios (startups; new entrants) are at a disadvantage in cross-licensing — they have nothing to offer in exchange; must build portfolios or pay cash.

Fabless companies (who design but do not manufacture chips) require specific patent strategies: FABLESS MODEL: design chips; outsource manufacturing to foundries (TSMC; Samsung Foundry; GlobalFoundries; SMIC); IP protection focuses on design; not manufacturing process; DESIGN IP PROTECTION: circuit architecture patents (what the chip does; how it is organized); algorithm patents (DSP algorithms; AI inference optimizations); interface and protocol implementations; memory subsystem designs; PROCESS IP: fabless companies typically do NOT own process patents (owned by the foundry); foundry provides process under a foundry agreement with process IP protections; fabless companies may own process-adjacent IP: specific design rule optimizations; device configurations achievable with the foundry's process; MASK WORK PROTECTION: the Semiconductor Chip Protection Act (SCPA) protects the specific physical layout (mask work) from direct copying; mask work registration at the US Copyright Office; 10-year protection; prevents direct layout copying but not independent design of same circuit; STANDARDS LICENSING EXPOSURE: fabless companies that implement wireless standards (Wi-Fi; 5G; Bluetooth) in their chips have SEP exposure; either need to cross-license or include SEP licensing pass-through from chip customers; ARM LICENSEES: companies that license ARM architecture pay per-chip royalties to ARM; these costs must be factored into chip pricing; STARTUP FABLESS STRATEGY: file patents on key design innovations before tapeout; provisional first; file before announcing the chip; focus on differentiating architecture rather than process technology; be aware of SEP licensing needs early — budget for them; ACQUISITION TARGETS: fabless companies with strong design IP portfolios are attractive acquisition targets; buyers value the portfolio + design team + customer relationships.

Standards-essential patents dominate licensing costs for wireless semiconductor implementations: THE WIRELESS STANDARDS ECOSYSTEM: 5G NR; 4G LTE; Wi-Fi 6/7 (IEEE 802.11ax/be); Bluetooth 5.x; USB 3.x/4; PCIe 5/6; NVMe; Ethernet 400G — each implemented through standards developed in standard-setting organizations (3GPP for cellular; IEEE for Wi-Fi/Ethernet/USB; JEDEC for memory); DECLARING ESSENTIAL PATENTS: companies that participate in SSOs disclose patents they believe may be essential to implementing the standard; these declared SEPs may or may not actually be essential (many declared SEPs are ultimately not technically essential); FRAND COMMITMENT: declaring essential status typically requires a FRAND licensing commitment; the company cannot refuse to license to anyone willing to pay FRAND rates; QUALCOMM'S LICENSING APPROACH (AND CONTROVERSY): Qualcomm charges royalties on the ENTIRE DEVICE PRICE (phone price) rather than on the chip price; critics: the patent's contribution should be valued at the chip level (the SSPPU), not the device level; Qualcomm: the patent enables the device's cellular functionality; FTC v. Qualcomm (N.D. Cal. 2019): found Qualcomm engaged in anticompetitive practices (reversed by 9th Circuit 2020); LICENSING COSTS FOR CHIP MAKERS: estimated total 5G SEP royalty stack: $10-$20 per handset from all SEP holders; individual SEP holder rates: Qualcomm (~3-5% of handset price); Ericsson; Nokia; InterDigital each ~0.5-2%; DESIGN-AROUND FOR SEPs: technically impossible for cellular standards (the standard mandates specific behavior that the SEP covers); for Wi-Fi: some room to implement non-standard optional features; STANDARD CONTRIBUTION STRATEGY: participate in SSO standard development; contribute patented technology to the standard; declare those patents as essential; collect FRAND royalties across the entire industry once the standard is adopted.

Semiconductor startups face specific patent risks that require proactive management: PRE-LAUNCH IP PROTECTION: file provisional patent applications before discussing the chip design with foundries, ODMs, or potential customers; under NDA is insufficient protection — file before disclosure; key innovations to patent: novel circuit architectures; algorithms implemented in silicon; new memory cell designs; interface protocol optimizations; energy efficiency techniques; PRE-TAPEOUT FTO ANALYSIS: before committing to tapeout ($1M-$5M+), conduct a freedom-to-operate analysis for key circuit elements; identify potentially blocking patents from major players (Qualcomm; ARM; TSMC; Intel; Samsung; Synopsys; Cadence); FTO before tapeout is far cheaper than a design change after; SEP LICENSING BUDGET: for chips implementing wireless standards, budget for SEP licensing early; estimate total stack cost per chip; factor into chip pricing; discuss with counsel whether to approach SEP holders before commercial launch or wait until sales volume justifies their attention; FOUNDRY AGREEMENTS: review foundry process technology license carefully; understand what design rule information is proprietary; confirm the foundry's IP indemnification scope; understand customer indemnification limits; ARM/MIPS/RISC-V ARCHITECTURE LICENSING: if using a licensed ISA (ARM; MIPS), understand the per-chip royalty burden; RISC-V (open ISA) eliminates architecture licensing fees but offers less ecosystem support; PATENT PORTFOLIO BUILDING: aim for 3-10 patents covering core differentiating technology by Series A; more by Series B; investors value patent protection; acquirers value patent portfolios; DEFENSIVE PUBLICATION: for innovations that are too numerous to patent (minor optimizations; implementation details), consider defensive publication (IP.com; technical disclosure) to create prior art and preserve freedom to operate.