Semiconductor Manufacturing Patents

ASML has one of the most remarkable technology monopolies in the history of manufacturing — achieved through 30+ years of focused R&D; strategic acquisitions; and a patent portfolio that makes replication essentially impossible: ASML EUV LITHOGRAPHY PATENT MONOPOLY: SCALE: 5,000+ active patents worldwide covering every aspect of EUV (Extreme Ultraviolet) lithography technology; LIGHT SOURCE: specific laser-produced plasma (LPP) EUV light source (specific CO2 laser + tin droplet target + specific droplet generator; specific EUV collection optics with specific multilayer mirror geometry); Cymer acquisition (2013; $2.5B) brought key EUV light source patents; OPTICAL SYSTEM: specific collector mirror geometry (specific graded multilayer Mo/Si mirror for 13.5nm EUV reflection); specific EUV projection optics (all-reflective system; 6-mirror design for specific wavefront correction); specific aberration measurement + correction algorithm; specific mask pattern correction for EUV-specific aberrations; WAFER STAGE: specific active vibration isolation system; specific six-DOF wafer stage with specific electromagnetic direct drive; specific sub-nanometer stage positioning with specific interferometric control loop; specific overlay measurement algorithm; HIGH-NA EUV (ASML TWINSCAN EXE): specific high-NA (0.55 NA vs. 0.33 NA for prior EUV) anamorphic projection optics; specific new reticle stage required by 4× anamorphic magnification; specific focus control for smaller depth-of-field; MASK BLANK AND PELLICLE: specific EUV mask blank deposition (specific Mo/Si multilayer on low-thermal-expansion substrate); specific EUV pellicle (specific polysilicon membrane for protecting mask from contamination); WAFER AND DOSE CONTROL: specific dose homogeneity algorithm for EUV source power fluctuations; ECONOMIC IMPACT: each NXE:3600D (current EUV scanner) costs approximately $350M; each High-NA EXE:5000 costs $380M+; TSMC; Samsung; Intel are the three customers for leading-edge EUV tools; NO OTHER COMPANY CAN MAKE EUV TOOLS: Nikon and Canon have tried and failed; the patents; accumulated expertise; and supplier ecosystem make this essentially an unassailable monopoly.

The leading semiconductor foundries have built enormous patent portfolios around their unique fabrication processes — particularly around the transistor architectures; deposition techniques; and integration schemes that define each node: TSMC PROCESS TECHNOLOGY PATENTS: SCALE: 10,000+ process patents across all nodes; 3NM NODE (N3B/N3E): specific FinFET optimization (specific fin geometry; specific fin pitch; specific fin liner; specific replacement metal gate (RMG) process integration); TSMC N3E ENOM (enhanced 3nm for scale); 2NM NODE (N2): specific nanosheet GAAFET (Gate-All-Around FET) architecture — first TSMC GAA; specific nanosheet width + thickness for specific drive current + leakage tradeoff; specific inner spacer formation process for GAA; specific source/drain epitaxy in GAA context; specific high-κ dielectric + metal gate (HKMG) deposition for nanosheet GAA; BACKSIDE PDN (POWER DELIVERY NETWORK): specific backside PDN routing (specific wafer bonding + etching + metal fill sequence for backside power + ground rails); SAMSUNG FOUNDRY PATENTS: GAA LEADERSHIP: Samsung was first to mass-produce GAA at 3nm (MBCFET — Multi-Bridge Channel FET); specific nanosheet stacking; specific ribbon width optimization; specific DIBL (drain-induced barrier lowering) suppression in GAA; INTEL FOUNDRY (INTEL 18A) PATENTS: RIBBONFET: Intel's own GAA branding; specific RibbonFET nanosheet geometry (specific width + spacing + dielectric fill); POWERVIA BACKSIDE PDN: specific Intel backside power delivery process (specific direct bonding + backside metal layer integration); specific signal routing freed by backside power — enabling specific cell area reduction; INTEL 20A: specific EUVL integration at 2nm class; MATERIALS INNOVATION: specific high-bandgap channel materials (InGaAs; GeSn) for specific mobility improvement; specific 2D semiconductor channel materials (MoS2; WSe2); FAB PROCESS PATENTS MORE GENERALLY: deposition (ALD = atomic layer deposition; specific precursor chemistry for specific film); etch (specific plasma chemistry + endpoint detection); CMP (specific slurry + pad + polish regime).

The semiconductor equipment and materials supply chain is itself a multi-billion dollar patent ecosystem — and the major equipment companies have built formidable IP portfolios that underpin every leading-edge fab: APPLIED MATERIALS: SCALE: 15,000+ patents (one of the largest semiconductor equipment portfolios); DEPOSITION: specific PECVD (plasma-enhanced CVD) chamber design for specific film quality; specific ALD (atomic layer deposition) process chemistry for specific high-k dielectrics (HfO2; ZrO2; Al2O3); specific gap-fill CVD processes for specific high-aspect-ratio trench fill; specific epitaxy (specific SiGe source/drain growth for strained channel); ETCH: specific plasma etch chamber with specific RF power distribution; specific atomic layer etch (ALE) — specific ALD-cycle-limited etch for atomic precision; CMP: specific planarization process + slurry system; THIN-FILM TRANSISTOR: specific IGZO TFT deposition for specific display application; LAM RESEARCH: SCALE: 5,000+ patents; ETCH: specific high-aspect-ratio etch for specific deep trench (DRAM capacitor) + HAR NAND flash + contact formation; specific atomic layer etch (ALE) process; specific cryogenic etch for specific low-damage silicon etch; DEPOSITION: specific PECVD gap-fill; specific ALD conformality for specific 3D NAND; specific W/Mo metal fill for wordlines; KLA CORPORATION: SCALE: 5,000+ patents; INSPECTION: specific electron beam inspection (e-beam) for specific buried defect detection; specific laser-based optical inspection (specific scatterometry for critical dimension measurement; specific angular resolved scatterometry for pattern characterization); METROLOGY: specific optical CD (critical dimension) measurement via scatterometry; specific overlay measurement; specific wafer geometry measurement; DEFECT REVIEW: specific ADR (automatic defect review) SEM; PHOTORESIST COMPANIES: JSR: major photoresist company; specific chemically amplified resist (CAR) compositions for ArFi and EUV; specific PAG (photoacid generator) chemistry; SHIN-ETSU CHEMICAL: specific PMMA + CAR photoresist chemistry; specific EUV resist formulations; TOKYO OHKA KOGYO (TOK): specific EUV resist and developer chemistry; INPRIA (MERCK ACQUISITION): specific metal oxide EUV resist — higher etch resistance than polymer CAR; specific tin-oxide EUV resist formulation; specific EUV sensitivity + resolution + LWR trade-off optimization; DUPONT: specific DUV + EUV resist chemistry.

Advanced packaging has become one of the most patent-active areas in semiconductors as chiplets and heterogeneous integration have replaced monolithic scaling as the primary path to performance improvement: ADVANCED PACKAGING PATENT LANDSCAPE: TSMC CoWoS (CHIP ON WAFER ON SUBSTRATE): specific CoWoS-S (silicon interposer) process (specific RDL on silicon interposer + micro-bump interconnect between chiplets); specific CoWoS-R (RDL interposer); specific CoWoS-L (local silicon interconnect); specific die-to-wafer bonding alignment algorithm; specific electromigration-resistant micro-bump metallurgy; TSMC SoIC (SYSTEM ON INTEGRATED CHIPS): specific face-to-face direct bonding (Cu-Cu thermo-compression bonding; specific CMP surface preparation for <1nm roughness bond interface); INTEL FOVEROS 3D STACKING: specific active-to-active chiplet stacking; specific 3D Foveros Direct Cu-Cu face-to-face bonding; specific vertical through-silicon via (TSV) implementation; specific thermal management for stacked logic dies; AMD + TSMC 3D V-CACHE: specific SRAM cache stacking on top of CCD (core chiplet die); specific thermal interface material selection for 3D stack; specific face-to-back Cu-Cu bonding; SAMSUNG X-CUBE: specific SRAM stacking using TSV; HBM (HIGH BANDWIDTH MEMORY): specific HBM stack structure (4/8/12 DRAM dies + base die stacked with TSVs); specific micro-bump pitch; SK Hynix + Micron + Samsung: competing HBM patents; HBM3E + HBM4 architecture; CHIPLET STANDARDS: UCIe (Universal Chiplet Interconnect Express): specific die-to-die interface standard (Intel; AMD; Qualcomm; Samsung; TSMC; Google + more); specific physical + logical layer specification; ADVANCED PACKAGING STARTUP IP STRATEGY: FOCUS AREAS: specific novel die-to-die interconnect architecture (specific bonding process + specific interconnect density + specific signal integrity solution); specific new thermal management approach for stacked dies (specific integrated cooling structure); specific chiplet disaggregation and recomposition tooling; specific electrical testing methodology for known-good-die (KGD) in assembled chiplet package; TRADE SECRETS: specific bonding process parameters (temperature + pressure + time + atmosphere for Cu-Cu direct bonding); specific yield improvement techniques for wafer bonding; KEY FTO: TSMC CoWoS; Intel Foveros; AMD 3D V-Cache; HBM architecture (Hynix + Micron + Samsung); UCIe specification implementation.