Ferroelectric Transistor Patents

Ferroelectric transistor (FeFET) / hafnium-oxide ferroelectric patents cover HfO2-ferroelectric-material innovations; FeFET-memory innovations; negative-capacitance innovations; and endurance/reliability and CMOS-integration innovations — with IP held by ferroelectric-memory companies, foundries, and the academic groups that pioneered hafnia ferroelectricity (in a field using ferroelectric transistors for non-volatile memory and low-power logic). WHY FERROELECTRIC TRANSISTORS: ferroelectric materials hold a switchable electric POLARIZATION — a remembered state usable for non-volatile memory; but classic ferroelectrics (perovskites) were NOT compatible with modern silicon CMOS, limiting them; the 2011 discovery that HAFNIUM OXIDE (HfO2, already a standard CMOS gate material) can be made FERROELECTRIC reignited the field — it's CMOS-compatible, scalable to small nodes, and enables a FeFET (ferroelectric field-effect transistor): a fast, low-power, NON-VOLATILE one-transistor memory, plus new low-power logic and in-memory compute. MAJOR HOLDERS: FERROELECTRIC MEMORY COMPANY (FMC, spun out of NaMLab/GlobalFoundries — a leader in HfO2 FeFET IP), plus SONY, SK HYNIX, TSMC, INTEL, and academic/NaMLab/research IP. HfO2 ferroelectric materials, FeFET memory, negative capacitance, endurance/reliability, and CMOS integration are the core FeFET patent domains — and material/phase engineering, memory cells, negative-capacitance logic, and reliability are the open whitespace.

HfO2-ferroelectric-material innovations; FeFET-memory-cell innovations; multi-level/compute innovations; and array/integration innovations represent core ferroelectric-transistor patent domains — and the CMOS-compatible ferroelectric material and the memory transistor built from it are the foundational, high-value capabilities. HfO2-FERROELECTRIC-MATERIAL PATENTS: the breakthrough enabler — DOPED hafnium oxide (with Si, Zr/HZO, Al, La, etc.) engineered to stabilize the FERROELECTRIC crystal phase (the orthorhombic phase, not the common non-ferroelectric phases), plus film thickness, annealing, and electrodes; the ferroelectric-HfO2 material (composition/doping/phase stabilization/process) is core, foundational IP (getting reliable ferroelectricity in a CMOS-compatible film is the whole basis of the field). FeFET-MEMORY-CELL PATENTS: integrating ferroelectric HfO2 into a transistor GATE to make a one-transistor NON-VOLATILE memory cell — the polarization state sets the transistor threshold (read by current); FeFET cell design (fast, low-power, low-write-voltage, scalable) is core, high-value IP (a compact embedded/storage memory). MULTI-LEVEL / COMPUTE PATENTS: storing MULTIPLE levels per FeFET (analog/multi-bit) for density and for in-memory/NEUROMORPHIC compute (FeFETs as synaptic weights) — overlapping with AI accelerators; multi-level/compute FeFET methods are high-value, opening new applications. ARRAY / INTEGRATION PATENTS: arranging FeFETs into memory ARRAYS (and 3D/NAND-like structures) with peripheral circuits; array methods are valuable. HfO2 ferroelectric materials, FeFET memory cells, multi-level/compute, and arrays are the highest-value core IP because a reliable CMOS-compatible ferroelectric and the compact non-volatile transistor built from it are exactly what define the technology.

Negative-capacitance-logic innovations; endurance/retention/reliability innovations; CMOS-integration innovations; and scaling and characterization innovations represent additional ferroelectric-transistor patent domains — and low-power logic, fixing the reliability weaknesses, and integrating into real chips are where the technology proves out. NEGATIVE-CAPACITANCE PATENTS: a different use — exploiting the ferroelectric to create a 'NEGATIVE CAPACITANCE' effect that makes a transistor switch MORE STEEPLY (lower subthreshold swing) than the fundamental Boltzmann limit allows, enabling LOWER-VOLTAGE, lower-power LOGIC transistors (NCFET); negative-capacitance device methods are high-value, distinctive IP (a route to beyond-CMOS low-power logic — though still being proven). ENDURANCE / RETENTION / RELIABILITY PATENTS: the KEY weaknesses — limited write ENDURANCE (cycles before wear-out), charge TRAPPING and threshold drift, RETENTION loss, and read disturb; methods improving endurance/retention/reliability (material/interface engineering, programming schemes) are CRITICAL, high-value IP (reliability is what gates FeFET adoption — and HfO2 FeFETs historically struggle here). CMOS-INTEGRATION PATENTS: integrating ferroelectric HfO2 into standard CMOS process flows (front-end gate-stack or back-end), thermal-budget compatibility, and embedding in logic; CMOS-integration methods are high-value (CMOS compatibility is HfO2 ferroelectrics' whole advantage — realizing it in real fabs is key). SCALING / CHARACTERIZATION PATENTS: scaling FeFETs to small nodes, and characterization/screening; scaling methods are valuable. Negative-capacitance logic, endurance/reliability, CMOS integration, and scaling are the highest-value enabling IP because low-power logic, solved reliability, and real CMOS integration are exactly what turn hafnia ferroelectricity into deployable memory and logic.

Ferroelectric transistor startup IP strategy must navigate FMC's strong HfO2-FeFET position, the NaMLab/academic foundational hafnia-ferroelectric IP (the 2011 discovery and core material patents), foundry/IDM portfolios (TSMC/Intel/SK Hynix/Sony), classic-ferroelectric (perovskite) prior art (old — the HfO2 CMOS-compatible angle is the novelty), the material-vs-device-vs-application split (ferroelectric film, FeFET cell, negative-capacitance logic, compute), the endurance/reliability problem (the central weakness — and the richest defensible IP), the CMOS-integration imperative (the whole advantage — and where foundry partnership matters), the memory-vs-logic-vs-compute strategic choice, the capital/foundry dependence, and a landscape where material/phase engineering, FeFET cells, negative capacitance, reliability, and integration are the durable assets; understand that the core hafnia-ferroelectric discovery is foundationally patented, so the durable IP for newcomers is in material/phase/interface engineering (esp. for reliability), specific FeFET cell/array designs, negative-capacitance devices, multi-level/compute, and CMOS-integration — with reliability solutions and process know-how often the real moat, and that endurance/retention, CMOS-integration, performance, and foundry adoption matter as much as patents; identify whitespace in reliability, compute, and integration. FERROELECTRIC-TRANSISTOR STARTUP IP STRATEGY: HAFNIA DISCOVERY IS FOUNDATIONALLY PATENTED — MATERIAL/PHASE/INTERFACE ENGINEERING, FeFET CELLS, NEGATIVE CAPACITANCE, RELIABILITY, AND CMOS INTEGRATION ARE THE IP: patent material/doping/phase/interface engineering, FeFET cell/array designs, negative-capacitance devices, multi-level/compute, and reliability/integration methods; CHECK FMC + NaMLab/ACADEMIC FOUNDATIONAL IP: the HfO2-ferroelectric discovery and core patents (FMC/NaMLab) are foundational — analyze FTO and build on improvements (or license); ENDURANCE/RETENTION/RELIABILITY IS THE CENTRAL WEAKNESS AND RICHEST WHITESPACE: HfO2 FeFETs struggle with limited endurance, charge trapping, and retention — material/interface/programming solutions are high-value, defensible IP (solving reliability unlocks adoption); CMOS INTEGRATION IS THE WHOLE ADVANTAGE: HfO2's value is CMOS compatibility — process-integration IP (and foundry partnership) is essential and valuable; MEMORY VS LOGIC (NEGATIVE CAPACITANCE) VS COMPUTE IS A STRATEGIC CHOICE: FeFET non-volatile memory, negative-capacitance low-power logic, and multi-level in-memory/neuromorphic compute are different applications and IP; NEGATIVE CAPACITANCE IS DISTINCTIVE (BUT UNPROVEN) WHITESPACE: beating the Boltzmann switching limit for low-power logic is high-value if realized; MULTI-LEVEL/COMPUTE OPENS AI APPLICATIONS: FeFETs as analog synaptic weights for in-memory/neuromorphic compute is a valuable crossover; MATERIAL/PROCESS KNOW-HOW IS OFTEN THE MOAT: reliable ferroelectric-phase films and integration recipes (some trade-secret) are a real advantage; RELIABILITY/INTEGRATION/PERFORMANCE/FOUNDRY-ADOPTION MATTER AS MUCH AS PATENTS: endurance/retention, CMOS integration, performance, and foundry/customer adoption drive value; WHEN TO PATENT (OR KEEP SECRET): NOVEL MATERIAL/CELL/NEGATIVE-CAP/RELIABILITY/INTEGRATION WITH MEASURED PERFORMANCE: file (or trade-secret process recipes) once a method shows measured results (ferroelectric polarization/phase + memory window + endurance cycles + retention + write voltage/speed/power + subthreshold swing (NCFET) + integration/yield) — measured endurance/retention, memory window, and CMOS-integration/yield are the critical FeFET IP metrics; KEY FTO CHECKLIST: FMC HfO2 FeFET; NaMLab/academic foundational hafnia ferroelectricity; TSMC/Intel/SK Hynix/Sony portfolios; classic perovskite ferroelectric prior art; HfO2 ferroelectric material (doping Si/Zr-HZO/Al/La, orthorhombic-phase stabilization, anneal/electrodes); FeFET memory cell (1T non-volatile, write voltage/window); multi-level/in-memory/neuromorphic compute; negative-capacitance (NCFET/subthreshold swing); endurance/retention/charge-trapping/read-disturb; CMOS integration (front/back-end, thermal budget); array/3D; scaling/characterization; material/process know-how (trade-secret).