Analog In-Memory Computing Patents

Analog / in-memory computing (compute-in-memory, CIM) patents cover crossbar and analog-MAC innovations; memory-device innovations; ADC/DAC and peripheral-circuit innovations; and weight-precision, architecture, and digital-in-memory innovations — with IP held by AI-chip startups, memory-device firms, and research labs (in a field performing AI computation INSIDE the memory array to escape the von Neumann data-movement bottleneck that dominates AI energy). WHY IN-MEMORY COMPUTING: in conventional (von Neumann) chips, moving weights between memory and compute units burns most of the energy and limits AI inference; IN-MEMORY computing performs the multiply-accumulate (MAC) operations WHERE the weights are stored — using the physics of the memory array (Ohm's law for multiply, Kirchhoff's current summing for accumulate) — dramatically cutting data movement and energy-per-operation. MAJOR IN-MEMORY-COMPUTING PATENT HOLDERS: MYTHIC: analog compute in flash memory (analog matrix multiply in NOR-flash arrays). IBM RESEARCH: analog AI using phase-change memory (PCM) crossbars. d-MATRIX: DIGITAL in-memory compute (DIMC, SRAM-based) for inference — more precise than analog. TETRAMEM (RRAM/memristor crossbar), UNTETHER AI / AXELERA (at/in-memory), RAIN AI, ANALOG INFERENCE. Also Samsung/TSMC/SK Hynix (memory CIM), and academic memristor groups. Crossbar/analog-MAC, memory devices, ADC/peripherals, and weight-precision/architecture are the core in-memory-computing patent domains — and ADC-overhead reduction, weight precision/drift control, novel memory devices, and digital-in-memory are the open whitespace.

Crossbar-array and analog-MAC innovations; resistive/memristive memory-device innovations; weight-programming and precision innovations; and digital-in-memory innovations represent core in-memory-computing patent domains — and computing matrix multiplication in the analog domain accurately (despite device noise) is the central challenge. CROSSBAR-ARRAY / ANALOG-MAC PATENTS: the crossbar that performs matrix-vector multiply — input voltages on rows, weights stored as device conductances at crosspoints, output currents summed on columns (Ohm + Kirchhoff) — array architecture, signaling, and how the MAC is mapped; this is the core compute primitive. RESISTIVE / MEMRISTIVE MEMORY-DEVICE PATENTS: the analog memory element storing weights as conductance — RRAM/ReRAM (resistive, TetraMem), PCM (phase-change, IBM), flash/floating-gate (Mythic), MRAM, and ferroelectric (FeFET) — device materials, multi-level (multi-bit) storage, endurance, and retention; the device is composition-of-matter IP. WEIGHT-PROGRAMMING / PRECISION PATENTS: programming weights accurately and stably into noisy analog devices — write/verify schemes, handling device-to-device variation, conductance DRIFT (PCM/RRAM weights drift over time/temperature, hurting accuracy), and error/noise compensation; precision is the make-or-break analog problem. DIGITAL-IN-MEMORY PATENTS: performing MAC digitally inside SRAM/memory (d-Matrix DIMC) — avoiding analog noise/ADC at some density cost, bit-serial schemes, and SRAM-based compute cells; a key alternative to analog. The crossbar analog-MAC, the analog memory device (RRAM/PCM/flash), and weight-precision/drift control are the highest-value device-level IP because the analog memory physics and precision determine whether in-memory computing is accurate enough to use.

ADC/DAC and peripheral-circuit innovations; mixed-signal and noise-management innovations; architecture and dataflow innovations; and energy-efficiency and mapping innovations represent additional in-memory-computing patent domains — and the data CONVERTERS and surrounding circuits (not the memory) often dominate power/area, so the periphery is where much of the real IP lives. ADC/DAC / PERIPHERAL-CIRCUIT PATENTS: converting analog crossbar currents back to digital (ADC) and inputs to analog (DAC) — the ADC is frequently the DOMINANT power/area cost of analog CIM, so low-power/low-area ADC designs, ADC sharing/time-multiplexing, and reduced-resolution schemes are extremely high-value IP. MIXED-SIGNAL / NOISE-MANAGEMENT PATENTS: managing analog noise, offset, temperature, and nonlinearity — calibration, reference schemes, and noise-aware training/quantization so models tolerate analog imprecision. ARCHITECTURE / DATAFLOW PATENTS: tiling crossbars into a full accelerator — mapping neural-network layers onto tiles, interconnect/network-on-chip, weight loading, pipelining, and supporting transformers/attention (not just CNNs) and large-model inference. ENERGY-EFFICIENCY / MAPPING PATENTS: maximizing TOPS/W and utilization — sparsity exploitation, model-to-hardware mapping/compiler, mixed analog-digital partitioning, and supporting required precision (INT8/FP) for accuracy. Low-power ADC/converter design (the dominant cost), noise/precision management enabling usable accuracy, and architecture/mapping for modern models (transformers) are the highest-value system-level IP because converters, accuracy, and model support determine whether in-memory computing delivers real efficiency on real workloads.

Analog in-memory computing startup IP strategy must navigate Mythic/IBM/d-Matrix/memristor portfolios, decades of crossbar and memristor prior art (analog crossbar computing and memristors have been researched extensively since the 2000s), the ADC-overhead, weight-precision/drift, and accuracy challenges, the model-support (transformer) and software/compiler realities, the memory-device manufacturability and foundry-access constraints, and a landscape where memory devices, crossbar/analog-MAC, ADC/peripherals, precision management, and architecture are the durable assets; understand that the basic crossbar/memristor MAC concept is well-trodden, so the durable IP is in low-power ADCs, weight-precision/drift control, novel manufacturable memory devices, digital-in-memory, and architecture/compilers for modern models, and that accuracy, ADC efficiency, model support, and software matter as much as patents; identify whitespace in ADC reduction, precision/drift, and transformer support. IN-MEMORY-COMPUTING STARTUP IP STRATEGY: BASIC CROSSBAR/MEMRISTOR MAC IS WELL-TRODDEN — ADCs, PRECISION, AND ARCHITECTURE ARE THE IP: analog crossbar computing has dense prior art, so patent low-power ADCs, weight-precision/drift control, novel devices, and architecture/mapping — not 'a crossbar that does MAC'; ADC/CONVERTER OVERHEAD IS THE DOMINANT COST AND HIGHEST-VALUE WHITESPACE: the ADC often dominates analog-CIM power/area — reducing/sharing/simplifying converters is the most valuable, defensible IP; WEIGHT PRECISION AND DRIFT ARE EXISTENTIAL FOR ACCURACY: analog device noise/variation/drift (esp PCM/RRAM) limit accuracy — programming/calibration/noise-aware-training IP is make-or-break; DIGITAL-IN-MEMORY IS A REAL ALTERNATIVE STRATEGY: SRAM-based DIMC (d-Matrix) trades density for precision/manufacturability — a distinct, patentable path avoiding analog/ADC pain; TRANSFORMER/LLM SUPPORT IS THE MODERN REQUIREMENT: early CIM targeted CNNs; supporting attention/transformers and large-model inference is where the market is — architecture/mapping IP for modern models is high-value; SOFTWARE/COMPILER AND MODEL MAPPING DETERMINE USABILITY: mapping models to noisy hardware (compiler, quantization, noise-aware training) is essential and patentable; MANUFACTURABILITY/FOUNDRY ACCESS GATES NOVEL DEVICES: exotic memory devices must be foundry-manufacturable — CMOS-compatible/embeddable devices win; WHEN TO PATENT: NOVEL DEVICE/CIRCUIT/ARCHITECTURE WITH MEASURED EFFICIENCY: file once a device/ADC/architecture shows measured results (TOPS/W + accuracy (vs digital baseline, INT8/FP) + ADC power/area fraction + weight precision/drift + model support (transformer) + manufacturability) vs. GPU/digital-accelerator baselines — measured TOPS/W, accuracy retention, and ADC efficiency are the critical in-memory-computing IP metrics; KEY FTO CHECKLIST: Mythic analog NOR-flash compute; IBM PCM analog AI crossbar; d-Matrix DIMC SRAM digital-in-memory; TetraMem RRAM memristor crossbar; Untether/Axelera at/in-memory; crossbar analog-MAC Ohm/Kirchhoff; RRAM/PCM/flash/MRAM/FeFET analog memory device multi-level; weight programming/write-verify/drift/variation compensation; ADC/DAC low-power/sharing/reduced-resolution; mixed-signal noise/calibration/noise-aware-training; architecture tiling/NoC/transformer-mapping; TOPS/W sparsity/mapping/compiler; memristor/crossbar prior art; foundry CMOS-compatibility.