Molybdenum Disulfide Transistor Patents

Molybdenum disulfide transistor patents cover material/growth innovations; contact innovations; gate-dielectric/device innovations; and integration innovations — with IP held by universities, research institutes, and semiconductor foundries/firms. WHY MoS2 / 2D TRANSISTORS: a MoS2 TRANSISTOR is a field-effect transistor (FET) whose SEMICONDUCTOR CHANNEL is an atomically-thin (MONOLAYER or few-layer) sheet of MOLYBDENUM DISULFIDE (MoS2) — a 2D TRANSITION-METAL DICHALCOGENIDE (TMD), one of the family of layered crystals (MoS2, WS2, WSe2, MoSe2) held together by weak van der Waals forces between atomic planes; the decisive contrast is with GRAPHENE, which is a SEMIMETAL with NO BANDGAP — graphene conducts beautifully but cannot be switched fully OFF, making it a poor digital transistor — whereas MONOLAYER MoS2 has a real, sizable BANDGAP (~1.8 eV, and DIRECT in the monolayer), so it CAN be turned off, giving low OFF-state leakage and a high ON/OFF ratio; because the channel is literally one molecular layer thin (~0.65 nm), the gate exerts near-ideal ELECTROSTATIC control over the channel, which suppresses the SHORT-CHANNEL EFFECTS that plague silicon at very small dimensions — so 2D FETs are studied as a route to ULTRA-SCALED, low-power transistors below the channel lengths where silicon falters, a candidate path BEYOND silicon CMOS scaling (and for BEOL/monolithic-3D logic layered atop silicon); the brutal HARD PROBLEMS, roughly in order of pain: WAFER-SCALE GROWTH (synthesizing uniform, low-defect, single-crystal-like MONOLAYER MoS2 across an entire wafer — typically by CVD or MOCVD — and transferring it without tears, wrinkles, or contamination), CONTACTS (making LOW-RESISTANCE electrical contacts to an atom-thin semiconductor — Schottky barriers and high CONTACT RESISTANCE are THE dominant, make-or-break challenge and the HEART of the field), GATE DIELECTRIC (depositing a high-quality high-k gate dielectric onto an INERT, dangling-bond-free 2D surface that resists conventional ALD nucleation), and INTEGRATION (low-temperature back-end-of-line / MONOLITHIC-3D integration on silicon CMOS, and building real circuits). MAJOR PLAYERS / RESEARCH LEADERS: academia and research institutes (MIT, STANFORD, EPFL — the Andras Kis group, IMEC) pioneering MoS2 FETs and wafer-scale growth, plus foundries/firms researching 2D FETs (TSMC, INTEL, SAMSUNG) evaluating 2D channels for future nodes and monolithic-3D. Material/growth, contacts, gate-dielectric/device, and integration are the core MoS2-transistor patent domains. HONEST FRAMING: MoS2 and 2D-TMD transistors are still largely PRE-COMMERCIAL and R&D-stage — a research frontier under active study, NOT a shipping commercial product. (Note: the MATERIAL/grown film (composition), the DEVICE structure, and the PROCESSES are §101-RESILIENT — so claim growth, contacts, dielectric/device, and integration.)

Material/growth innovations; contact innovations; wafer-scale-MoS2 innovations; and low-contact-resistance innovations represent core molybdenum disulfide transistor patent domains — and the material/growth (the substrate of everything) and the contacts (the heart, the dominant challenge) are the foundational, high-value, §101-resilient capabilities. MATERIAL / GROWTH PATENTS: the FOUNDATION — WAFER-SCALE MONOLAYER MoS2 (growing uniform, large-area, single-crystal or quasi-single-crystal MONOLAYER MoS2 across a full wafer — the precondition for any manufacturable 2D FET), CVD / MOCVD (chemical-vapor / metal-organic CVD growth chemistries, precursors, seeding, nucleation control, and grain-boundary minimization to get continuous low-defect film), TRANSFER (releasing the grown monolayer and transferring it onto a device wafer without tears, wrinkles, polymer residue, or doping contamination — or direct epitaxial growth that avoids transfer), and DEFECTS (sulfur vacancies and grain boundaries that scatter carriers and pin the Fermi level — passivation and defect-engineering); growth methods are core, high-value, DISTINCTIVE composition/process IP, §101-resilient (wafer-scale monolayer MoS2 by CVD/MOCVD, clean transfer, and defect control are central, contested, defensible IP, since without uniform low-defect monolayer film over a wafer there is no manufacturable transistor). CONTACT PATENTS: the HEART — the single most important, make-or-break problem — CONTACT RESISTANCE (the dominant challenge: metal-to-MoS2 junctions form SCHOTTKY BARRIERS and Fermi-level pinning that throttle current and dominate device resistance at scale — so LOW-RESISTANCE contact schemes are the most contested IP in the field), SEMIMETAL CONTACTS (using semimetals such as BISMUTH or ANTIMONY whose density of states suppresses the Schottky barrier and approaches the quantum limit of contact resistance — a landmark direction), PHASE-ENGINEERED CONTACTS (locally converting the semiconducting 2H phase of MoS2 to the metallic 1T phase under the contact for a low-barrier 2D-2D junction), and EDGE/DOPED CONTACTS (edge-contact geometries and contact-region doping); contact methods are core, high-value, DISTINCTIVE composition/process IP, §101-resilient (LOW CONTACT RESISTANCE via SEMIMETAL and PHASE-ENGINEERED contacts is the central, contested, defensible IP, because contact resistance — not the channel — is what currently limits MoS2 FET performance, so whoever owns good contacts owns the bottleneck). WAFER-SCALE-MoS2 PATENTS: large-area uniform monolayer growth/transfer; wafer-scale methods are high-value composition/process IP, §101-resilient (manufacturable area is the gate to commercialization). LOW-CONTACT-RESISTANCE PATENTS: semimetal/phase-engineered/doped low-resistance contacts; low-contact-resistance methods are high-value composition/process IP, §101-resilient (the contact is the bottleneck). Material/growth, contacts, wafer-scale-MoS2, and low-contact-resistance are the highest-value core IP because uniform wafer-scale monolayer film and low-resistance contacts are exactly what stand between a lab MoS2 device and a manufacturable transistor.

Gate-dielectric/device innovations; integration innovations; high-k-on-2D innovations; and monolithic-3D innovations represent additional molybdenum disulfide transistor patent domains — and the gate dielectric/device (the control) and the integration (the path to a chip) turn a grown film and good contacts into a working, manufacturable transistor and circuit. GATE-DIELECTRIC / DEVICE PATENTS: the CONTROL — DIELECTRIC INTEGRATION (the distinctive 2D problem: an ideal MoS2 surface is chemically INERT and DANGLING-BOND-FREE, so conventional ALD of a high-k dielectric (HfO2, Al2O3) does not NUCLEATE uniformly — methods to seed/functionalize the surface, use native or van-der-Waals dielectrics like hexagonal boron nitride (hBN), or deposit pinhole-free high-k without damaging the monolayer are core IP), DEVICE ARCHITECTURE (top-gate, bottom-gate, dual-gate, and gate-all-around / stacked-nanosheet 2D geometries, plus encapsulation to protect the monolayer), and INTERFACE QUALITY (minimizing interface traps and hysteresis that degrade subthreshold swing and stability); dielectric/device methods are core, high-value, DISTINCTIVE process/device IP, §101-resilient (HIGH-K-ON-2D dielectric integration and device architecture are central, contested, defensible IP, since you cannot get the steep, low-leakage switching MoS2 promises without a clean, thin, pinhole-free gate stack on an unreactive 2D surface — a problem with no silicon analog). INTEGRATION PATENTS: the PATH TO A CHIP — BEOL / MONOLITHIC-3D INTEGRATION (the strategic prize: because 2D FETs can be processed at LOW TEMPERATURE, they can be built in the BACK-END-OF-LINE on TOP of finished silicon CMOS — enabling MONOLITHIC 3D stacking of logic/memory without thermally damaging the silicon below), CMOS INTEGRATION (n-type MoS2 with a complementary p-type 2D channel (e.g., WSe2) to make CMOS-style 2D logic, and co-integration with silicon), and CIRCUITS (demonstrating inverters, ring oscillators, SRAM, and larger functional circuits in 2D — the proof that devices compose into systems); integration methods are core, high-value, DISTINCTIVE process IP, §101-resilient when tied to the structure (BEOL / MONOLITHIC-3D integration on silicon CMOS is core, contested, defensible IP, because the realistic near-term value of 2D FETs is as a low-temperature BEOL layer stacked on silicon — monolithic 3D — not as a wholesale silicon replacement). HIGH-K-ON-2D PATENTS: ALD seeding / vdW dielectrics / hBN gate stacks; high-k-on-2D methods are high-value process IP, §101-resilient (the gate stack is the control problem). MONOLITHIC-3D PATENTS: low-temperature BEOL 2D-on-silicon stacking; monolithic-3D methods are high-value process IP, §101-resilient when tied to the structure (3D stacking is the near-term prize). Gate-dielectric/device, integration, high-k-on-2D, and monolithic-3D are the highest-value IP because a clean gate stack and low-temperature 3D integration on silicon are what convert a 2D channel into a real, manufacturable, stackable transistor.

Molybdenum disulfide transistor startup IP strategy must navigate the material-device-and-process-are-§101-resilient (MoS2 FET IP is MATERIAL/grown-film (composition), DEVICE structure, and PROCESS IP — strongly §101-RESILIENT — so growth, contact, dielectric/device, and integration claims are strong, unlike software/abstract-idea claims), the contacts-are-the-central-make-or-break (CONTACT RESISTANCE — Schottky barriers and Fermi-level pinning at the metal/MoS2 junction — is THE dominant problem and currently limits device performance far more than the channel, so SEMIMETAL (bismuth/antimony) and PHASE-ENGINEERED low-resistance contacts are the single most decisive IP, the heart of the field), the wafer-scale-growth-is-the-other-make-or-break (there is no manufacturable transistor without uniform, low-defect MONOLAYER MoS2 grown over a full wafer by CVD/MOCVD and transferred/grown cleanly — so wafer-scale growth and clean transfer are the second central make-or-break and a true manufacturability gate), the high-k-on-an-inert-2D-surface-is-a-distinctive-hard-problem (the ideal MoS2 surface is dangling-bond-free so conventional ALD will not nucleate — clean, thin, pinhole-free GATE DIELECTRIC integration (seeding, vdW dielectrics, hBN) is a hard problem with NO silicon analog and is defensible IP), the monolithic-3D-BEOL-on-silicon-is-the-realistic-near-term-value (the credible near-term prize is NOT replacing silicon wholesale but using low-temperature 2D FETs as a BACK-END-OF-LINE / MONOLITHIC-3D layer stacked on top of finished CMOS — so frame the company around 3D integration and complementing silicon, not beating it head-to-head), the this-is-pre-commercial-R&D-stage-so-be-honest (MoS2/2D FETs are a RESEARCH FRONTIER, still largely pre-commercial — timelines are long, capital is heavy, and most value today is demonstrated metrics and IP, not revenue — investors and partners must be told this honestly), the foundry-and-academic-incumbents-dominate-the-art (MIT, Stanford, EPFL/Andras Kis, imec on the academic side and TSMC, Intel, Samsung on the foundry side hold significant, fast-moving 2D-FET IP — so a startup needs a genuinely novel contact/growth/dielectric/integration edge and rigorous FTO), the metrics-decide (contact resistance (Ω·μm), mobility, ON/OFF ratio, subthreshold swing, wafer-scale uniformity/yield, and BEOL-compatible thermal budget are what prove a 2D FET — demonstrated, measured device data is decisive, more than patents alone), the licensing-and-partnership-models (a startup can be a MATERIALS/growth company, a CONTACT/process-IP licensor, a tool/integration enabler, or a device/circuit demonstrator — the model is a key strategic choice with different IP), and the platform-not-just-MoS2 (the contact, growth, dielectric, and integration techniques often generalize across the TMD family (WS2, WSe2, MoSe2) — claim broadly across 2D TMDs where the data supports it, not MoS2 alone); understand that contacts and wafer-scale growth are the central make-or-break, so the durable startup IP is in low-resistance (semimetal/phase-engineered) contacts, wafer-scale monolithic-quality growth/transfer, high-k-on-2D dielectric integration, and low-temperature monolithic-3D BEOL integration on silicon — with low-resistance contacts and manufacturable wafer-scale film often the real moat, and that §101-resilient material/device/process IP, demonstrated device metrics, and FTO matter as much as patents; identify whitespace in contacts, growth/transfer, dielectric integration, and 3D integration. MOLYBDENUM DISULFIDE TRANSISTOR STARTUP IP STRATEGY: MATERIAL/GROWTH, CONTACTS, GATE-DIELECTRIC/DEVICE, AND INTEGRATION ARE THE IP: patent growth, contacts, dielectric/device, and integration — composition + device + process claims (§101-resilient); MATERIAL-DEVICE-AND-PROCESS-ARE-§101-RESILIENT: MATERIAL (composition) + DEVICE structure + PROCESS IP — strongly §101-RESILIENT; CONTACTS-ARE-THE-CENTRAL-MAKE-OR-BREAK: CONTACT RESISTANCE (Schottky barriers / Fermi-level pinning) is THE dominant problem — SEMIMETAL (bismuth/antimony) + PHASE-ENGINEERED contacts the single most decisive IP, the heart; WAFER-SCALE-GROWTH-IS-THE-OTHER-MAKE-OR-BREAK: uniform low-defect MONOLAYER MoS2 over a full wafer by CVD/MOCVD + clean transfer/growth — the manufacturability gate; HIGH-K-ON-AN-INERT-2D-SURFACE-IS-A-DISTINCTIVE-HARD-PROBLEM: dangling-bond-free MoS2 resists ALD nucleation — clean pinhole-free GATE DIELECTRIC (seeding/vdW/hBN) a hard problem with NO silicon analog; MONOLITHIC-3D-BEOL-ON-SILICON-IS-THE-REALISTIC-NEAR-TERM-VALUE: low-temperature 2D FETs as a BEOL / MONOLITHIC-3D layer on finished CMOS — complement silicon, don't beat it head-to-head; THIS-IS-PRE-COMMERCIAL-R&D-STAGE-SO-BE-HONEST: a RESEARCH FRONTIER, still largely pre-commercial — long timelines, heavy capital, value today is metrics + IP not revenue; FOUNDRY-AND-ACADEMIC-INCUMBENTS-DOMINATE-THE-ART: MIT/Stanford/EPFL(Andras Kis)/imec + TSMC/Intel/Samsung hold significant fast-moving 2D-FET IP — need a novel edge + FTO; METRICS-DECIDE: contact resistance (Ω·μm)/mobility/ON-OFF ratio/subthreshold swing/wafer uniformity/yield/BEOL thermal budget — measured device data decisive; LICENSING-AND-PARTNERSHIP-MODELS: MATERIALS/growth, CONTACT/process licensor, integration enabler, or device/circuit demonstrator — a key choice; PLATFORM-NOT-JUST-MoS2: techniques generalize across TMDs (WS2/WSe2/MoSe2) — claim broadly across 2D TMDs where data supports; WHEN TO PATENT: NOVEL GROWTH/CONTACT/DIELECTRIC/INTEGRATION WITH DATA: file once it shows data (wafer-scale film + low-resistance contact + gate stack + BEOL integration) — composition + device + process claims; demonstrated contact resistance, mobility, ON/OFF, subthreshold swing, wafer uniformity, and thermal budget are the critical MoS2-FET IP metrics; KEY FTO CHECKLIST: MIT/Stanford/EPFL(Andras Kis)/imec + TSMC/Intel/Samsung; material/growth (WAFER-SCALE MONOLAYER MoS2/CVD-MOCVD/clean TRANSFER/DEFECT-sulfur-vacancy control — §101-resilient, the foundation); contacts (CONTACT RESISTANCE/SEMIMETAL bismuth-antimony/PHASE-ENGINEERED 1T/edge-doped — §101-resilient, the central make-or-break, the heart); wafer-scale-MoS2; low-contact-resistance (the bottleneck); gate-dielectric/device (HIGH-K-ON-2D ALD-seeding-vdW-hBN/DEVICE ARCHITECTURE gate-all-around/interface quality — §101-resilient, the control, no silicon analog); integration (BEOL/MONOLITHIC-3D-on-silicon/CMOS n-MoS2-p-WSe2/CIRCUITS — tie to structure, the near-term prize); high-k-on-2D; monolithic-3D (the near-term prize); material/device + process the §101-resilient strength; contacts the central make-or-break and the heart; wafer-scale growth the other make-or-break; high-k-on-an-inert-2D-surface a distinctive hard problem with no silicon analog; monolithic-3D BEOL on silicon the realistic near-term value; this is pre-commercial R&D-stage so be honest; foundry + academic incumbents dominate the art; metrics decide; licensing + partnership models; platform not just MoS2 (generalize across TMDs).