DRAM — The Memory in Every Computer, Phone, and Server
Robert Dennard's 1968 IBM patent describes dynamic random-access memory (DRAM) — the one-transistor-one-capacitor memory cell that became the dominant form of computer RAM, scaling from kilobytes to terabytes over 50 years.
Original patent title: “Field-effect transistor memory”
What this patent covers
The actual claim
This patent describes a memory cell consisting of a single transistor and a single capacitor. The capacitor stores one bit of data as an electrical charge (charged = 1, uncharged = 0). The transistor acts as a switch: to read the stored bit, the transistor is switched on, allowing the capacitor's charge (or lack of charge) to flow to a sense amplifier; to write a bit, the transistor is switched on and the capacitor is charged or discharged to the desired value. Because the capacitor gradually loses its charge over milliseconds (it 'leaks'), the memory must be periodically refreshed — hence 'dynamic' RAM. This periodic refresh is the tradeoff for using just one transistor and one capacitor per bit, making DRAM far denser than SRAM (which uses 6 transistors per bit).
What this patent does NOT cover
The boundaries
- SRAM (Static RAM) — a different memory cell architecture using 6 transistors per bit, no refresh needed, faster but less dense
- NAND Flash memory — a non-volatile storage technology (data persists without power), covered in a separate patent
- Memory controllers and refresh circuits — the patent covers the individual cell, not the surrounding circuitry
- Specific DRAM variants (DDR, LPDDR, HBM) — all use the 1T-1C cell principle but add different bus interfaces and timing
These exclusions are unique to PatentBrief — derived from the actual claim language, not patent-office boilerplate.
What made this novel
Before DRAM, computer memory was either magnetic core memory (expensive, slow, large) or SRAM (using 6 transistors per bit, which was expensive and large). Dennard's insight was radical simplicity: why use 6 transistors if you can store the bit in a capacitor and use just 1 transistor to access it? The tradeoff — needing to periodically refresh the capacitor to prevent data loss — was solvable in hardware. The resulting 1T-1C cell was so small that memory density could scale dramatically. Dennard also formulated 'Dennard Scaling' — the observation that as transistors shrink, power consumption scales proportionally, meaning smaller chips run cooler. This law held from the 1970s until the mid-2000s, driving 40 years of Moore's Law improvements.
Schematic visualization of the patent's claim structure. Hand-drawn diagrams in progress for each landmark patent.
Where you've seen this
Real-world examples
The first commercial DRAM chip was Intel's 1103 (1970), which stored 1 kilobit — 1,024 bits — and replaced magnetic core memory in minicomputers
Modern DRAM (DDR5) stores tens of gigabytes on chips built from billions of Dennard's 1T-1C cells, using nanometer-scale fabrication
Every server in AWS, Google, and Microsoft's data centers uses DRAM as working memory — global DRAM production exceeds $80 billion per year
Why it matters
The bigger picture
DRAM is the reason computers can hold gigabytes of data in active memory at affordable prices. Dennard never received royalties — IBM owned the patent and cross-licensed it as part of industry-wide agreements. He went on to identify 'Dennard Scaling,' which predicted how transistor miniaturization would drive power efficiency improvements — until it stopped working around 2006 when quantum effects began limiting further scaling. The end of Dennard scaling is one reason CPU clock speeds plateaued in the mid-2000s and manufacturers turned to multi-core processors instead. DRAM itself continues to scale through extreme ultraviolet lithography and 3D stacking (HBM), but the fundamental 1T-1C cell Dennard patented in 1968 remains the basis of all of it.
Filed
July 14, 1967
Granted
June 4, 1968
Claim 1 — Plain English
What this patent covers
This patent describes a memory cell consisting of a single transistor and a single capacitor. The capacitor stores one bit of data as an electrical charge (charged = 1, uncharged = 0). The transistor acts as a switch: to read the stored bit, the transistor is switched on, allowing the capacitor's charge (or lack of charge) to flow to a sense amplifier; to write a bit, the transistor is switched on and the capacitor is charged or discharged to the desired value. Because the capacitor gradually loses its charge over milliseconds (it 'leaks'), the memory must be periodically refreshed — hence 'dynamic' RAM. This periodic refresh is the tradeoff for using just one transistor and one capacitor per bit, making DRAM far denser than SRAM (which uses 6 transistors per bit).
The clever bit
Before DRAM, computer memory was either magnetic core memory (expensive, slow, large) or SRAM (using 6 transistors per bit, which was expensive and large). Dennard's insight was radical simplicity: why use 6 transistors if you can store the bit in a capacitor and use just 1 transistor to access it? The tradeoff — needing to periodically refresh the capacitor to prevent data loss — was solvable in hardware. The resulting 1T-1C cell was so small that memory density could scale dramatically. Dennard also formulated 'Dennard Scaling' — the observation that as transistors shrink, power consumption scales proportionally, meaning smaller chips run cooler. This law held from the 1970s until the mid-2000s, driving 40 years of Moore's Law improvements.
What it does not cover
- SRAM (Static RAM) — a different memory cell architecture using 6 transistors per bit, no refresh needed, faster but less dense
- NAND Flash memory — a non-volatile storage technology (data persists without power), covered in a separate patent
- Memory controllers and refresh circuits — the patent covers the individual cell, not the surrounding circuitry
- Specific DRAM variants (DDR, LPDDR, HBM) — all use the 1T-1C cell principle but add different bus interfaces and timing
Patent Journey
From filing to expiry
Patent Filed
1967
Patent Granted
1968 · 1yr after filing
Highly Cited
191 patents cite this
Patent Expired
1987
PatentBrief Score
Impact Score
Moderate
Citation count
40/40
Highly cited
Claim breadth
0/20
Narrow claims
Recency
0/20
Older than 20 years
Assignee scale
0/20
Independent or smaller assignee
PatentBrief Impact Score — based on citation count, claim breadth, recency, and assignee scale. Not a legal assessment.
Glossary
Key terms defined
- refresh
- The periodic operation of recharging DRAM capacitors before they lose their charge — happens thousands of times per second
- capacitor
- An electronic component that stores electrical charge — in a DRAM cell, charge presence = 1, absence = 0
- 1T-1C cell
- One Transistor, One Capacitor — the fundamental DRAM memory cell structure described in this patent
- volatile memory
- Memory that loses its contents when power is removed — all DRAM is volatile, unlike flash storage
Citations
Patent lineage
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