# How to Program 3D Layered Memory Chips More Precisely > This patent describes a method for precisely programming the control transistors and memory cells in advanced 3D non-volatile memory chips, ensuring reliable data storage in stacked layers. - **Patent:** US 9947413 - **Original title:** Method of initializing and programming 3D non-volatile memory device - **Owner:** Seoul National University R&DB Foundation - **Granted:** 2018 - **Status:** Active - **Times cited:** 0 - **Field:** consumer_electronics, semiconductors, telecommunications, software ## What it does This patent details a method for setting up and programming 3D non-volatile memory devices, which are like tiny, layered data storage cities. First, it applies a specific voltage (a "first program voltage") to a "selected string selection line" (a control wire) in a chosen memory layer (Claim 1). Then, it checks if the "string selection transistors" (SSTs, which are like gates for memory strings) connected to that wire have reached a target "threshold voltage" (the voltage needed to turn them on). This check identifies which SSTs are already "programmed" and which are "unprogrammed" (Claim 1). Next, it programs the actual "memory cell transistors" (MCTs) within the memory strings that are coupled with the *programmed* SSTs. These MCTs are set to a specific threshold voltage so they can function as "screening transistors" (Claim 1). Finally, it uses these newly programmed MCTs to block programming to the channel lines of the *programmed* SSTs, while a "third program voltage" is applied to the selected string selection line to *selectively program* only the *unprogrammed* SSTs (Claim 1). This ensures precise control over which parts of the memory are programmed. ## What it does NOT cover - Does not cover programming methods for traditional 2D (planar) non-volatile memory structures. - Does not cover programming string selection transistors without an intermediate verification step to distinguish programmed from unprogrammed ones. - Does not cover programming memory cell transistors without using them as screening transistors for subsequent string selection transistor programming. - Does not cover memory architectures that do not include distinct string selection lines, wordlines, and channel lines in a 3D arrangement. - Does not cover programming techniques that do not involve applying a first, second, and third program voltage in the specified sequence. ## The clever bit The novelty lies in the two-stage programming of string selection transistors, specifically by using *already programmed memory cell transistors* as "screening transistors" to selectively block programming for certain paths while allowing others. This allows for more precise and controlled programming of the complex 3D stacked memory architecture. ## Real-world examples 1. Solid-state drives (SSDs) 2. Smartphone internal storage (eMMC, UFS) 3. USB flash drives 4. Enterprise data center storage 5. Memory cards (SD cards, microSD cards) 6. 3D NAND flash memory chips ## Why it matters 3D non-volatile memory, often called 3D NAND, is the backbone of modern data storage, found in solid-state drives (SSDs), smartphones, and data centers. As memory chips become denser by stacking layers, precise control over programming individual cells and their control transistors is critical. This method aims to improve the reliability and efficiency of these complex 3D structures, which directly impacts the performance and lifespan of storage devices. ## Frequently asked questions ### What does How to Program 3D Layered Memory Chips More Precisely cover? This patent describes a method for precisely programming the control transistors and memory cells in advanced 3D non-volatile memory chips, ensuring reliable data storage in stacked layers. ### Who owns patent US 9947413? Seoul National University R&DB Foundation owns this patent, granted in 2018. ### When does this patent expire? This patent is expected to expire on November 3, 2036, when the invention enters the public domain. ### What problem does this patent solve? 3D non-volatile memory, often called 3D NAND, is the backbone of modern data storage, found in solid-state drives (SSDs), smartphones, and data centers. As memory chips become denser by stacking layers, precise control over programming individual cells and their control transistors is critical. This method aims to improve the reliability and efficiency of these complex 3D structures, which directly impacts the performance and lifespan of storage devices. ### What does this patent NOT cover? Does not cover programming methods for traditional 2D (planar) non-volatile memory structures. **Full plain-English explainer:** https://patentbrief.org/patent/us/9947413/method-of-initializing-and-programming-3d-non-volatile-memory-device **Original patent:** https://patents.google.com/patent/US9947413 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How to Prepare 3D Flash Memory for Use](https://patentbrief.org/patent/us/9685235/method-of-initializing-3d-non-volatile-memory-device) — This patent describes a method for setting up a 3D non-volatile memory chip, like those in SSDs, by precisely programming control transistors, including a special "dummy" one, to make sure the memory works correctly. - [How to Precisely Erase Data in 3D NAND Flash Memory](https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory) — This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed. - [How 3D Memory Chips Fix Tiny Flaws to Keep Working](https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory) — Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. - [How Multi-Level Cell Memory Stores More Data in Less Space](https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system) — Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming. - [How a Special Memory Chip Helps Fix Broken 3D NAND Storage](https://patentbrief.org/patent/us/12450117/firmware-repair-for-three-dimensional-nand-memory) — This patent describes a special content addressable memory (CAM) system that quickly finds and reroutes around defective memory locations in 3D NAND storage using multiple processing units at once.