# How to Stack Two Computer Chips with Direct Connections

> TSMC's patent describes a compact way to stack two computer chips directly on top of each other, using a special filling material to hold tiny electrical connections in place, often with the top chip being wider than the bottom.

- **Patent:** US 9412678
- **Original title:** Structure and method for 3D IC package
- **Owner:** Taiwan Semiconductor Manufacturing Co TSMC
- **Granted:** 2016
- **Status:** Active
- **Times cited:** 1
- **Field:** semiconductors, consumer_electronics, telecommunications, software, ai_ml

## What it does

The patent describes a way to build a compact chip package by stacking a "first die" (a semiconductor chip) and a "second die" directly. An "underfill" material is placed between these two chips, making physical contact with both (Claim 1). Inside this underfill, tiny "conductive elements" (like solder bumps or under-bump metallization) create electrical connections between the first and second dies (Claim 1, Claim 5). The first die also has "interconnection layers" on its back side, which connect to the conductive elements through "through-vias" that pass all the way through the first die's semiconductor material (Claim 1). This allows for a very dense, direct connection between stacked chips. For example, a smaller processor chip could be stacked directly on a wider memory chip, with the underfill and surrounding molding compounds providing mechanical support for the wider top chip (Claim 9).

## What it does NOT cover

- Chip packages where the electrical connections between stacked dies are not fully encapsulated within an underfill material (Claim 1).
- Stacking chips that rely on an intermediate "interposer" substrate to connect the dies, rather than direct die-to-die connections (Claim 14).
- Chip packages where the electrical connections from the lower die do not pass through "through-vias" to interconnection layers on the opposite side (Claim 1).
- Packages where the first and second dies are not physically in contact with the underfill (Claim 1).
- Chip stacking methods that do not use molding compounds to encapsulate the dies and underfill (Claim 2, Claim 8).

## The clever bit

The novelty lies in directly coupling two dies with conductive elements fully encapsulated in an underfill, combined with through-vias in the lower die connecting to external layers, and often supporting an "overhang" structure where the top chip is wider, all without an interposer. This creates a very compact and mechanically robust 3D package.

## Real-world examples

1. High-bandwidth memory (HBM) stacks
2. Advanced smartphone processors with integrated memory
3. Graphics processing units (GPUs)
4. System-on-chip (SoC) packages
5. Multi-chip modules (MCMs)

## Why it matters

This patent is significant for creating high-density, compact electronic devices. By stacking chips directly and using underfill to secure connections, it enables more powerful functions in smaller spaces. This approach is crucial for advanced packaging technologies, allowing for better performance and lower power consumption in complex integrated circuits. TSMC, a leading chip manufacturer, uses such techniques to produce chips for a wide range of consumer electronics and high-performance computing.

## Frequently asked questions

### What does How to Stack Two Computer Chips with Direct Connections cover?

TSMC's patent describes a compact way to stack two computer chips directly on top of each other, using a special filling material to hold tiny electrical connections in place, often with the top chip being wider than the bottom.

### Who owns patent US 9412678?

Taiwan Semiconductor Manufacturing Co TSMC owns this patent, granted in 2016.

### When does this patent expire?

This patent is expected to expire on March 20, 2035, when the invention enters the public domain.

### What is patent US 9412678 cited by?

This patent has been cited by 1 later patents that build on its ideas.

### What problem does this patent solve?

This patent is significant for creating high-density, compact electronic devices. By stacking chips directly and using underfill to secure connections, it enables more powerful functions in smaller spaces. This approach is crucial for advanced packaging technologies, allowing for better performance and lower power consumption in complex integrated circuits. TSMC, a leading chip manufacturer, uses such techniques to produce chips for a wide range of consumer electronics and high-performance computing.

### What does this patent NOT cover?

Chip packages where the electrical connections between stacked dies are not fully encapsulated within an underfill material (Claim 1).

**Full plain-English explainer:** https://patentbrief.org/patent/us/9412678/structure-and-method-for-3d-ic-package

**Original patent:** https://patents.google.com/patent/US9412678

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_Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._