{
  "patent_number": "US 9412678",
  "country": "US",
  "title": "How to Stack Two Computer Chips with Direct Connections",
  "original_title": "Structure and method for 3D IC package",
  "summary": "TSMC's patent describes a compact way to stack two computer chips directly on top of each other, using a special filling material to hold tiny electrical connections in place, often with the top chip being wider than the bottom.",
  "what_it_does": "The patent describes a way to build a compact chip package by stacking a \"first die\" (a semiconductor chip) and a \"second die\" directly. An \"underfill\" material is placed between these two chips, making physical contact with both (Claim 1). Inside this underfill, tiny \"conductive elements\" (like solder bumps or under-bump metallization) create electrical connections between the first and second dies (Claim 1, Claim 5). The first die also has \"interconnection layers\" on its back side, which connect to the conductive elements through \"through-vias\" that pass all the way through the first die's semiconductor material (Claim 1). This allows for a very dense, direct connection between stacked chips. For example, a smaller processor chip could be stacked directly on a wider memory chip, with the underfill and surrounding molding compounds providing mechanical support for the wider top chip (Claim 9).",
  "what_it_does_not_cover": [
    "Chip packages where the electrical connections between stacked dies are not fully encapsulated within an underfill material (Claim 1).",
    "Stacking chips that rely on an intermediate \"interposer\" substrate to connect the dies, rather than direct die-to-die connections (Claim 14).",
    "Chip packages where the electrical connections from the lower die do not pass through \"through-vias\" to interconnection layers on the opposite side (Claim 1).",
    "Packages where the first and second dies are not physically in contact with the underfill (Claim 1).",
    "Chip stacking methods that do not use molding compounds to encapsulate the dies and underfill (Claim 2, Claim 8)."
  ],
  "filed": "2015-03-20",
  "granted": "2016-08-09",
  "expires": "2035-03-20",
  "status": "active",
  "holder": "Taiwan Semiconductor Manufacturing Co TSMC",
  "holder_url": "https://patentbrief.org/company/taiwan-semiconductor-manufacturing-co-tsmc",
  "inventors": [
    {
      "name": "Chen-Hua Yu",
      "url": "https://patentbrief.org/inventor/chen-hua-yu"
    },
    {
      "name": "Der-Chyang Yeh",
      "url": "https://patentbrief.org/inventor/der-chyang-yeh"
    },
    {
      "name": "Shin-puu Jeng",
      "url": "https://patentbrief.org/inventor/shin-puu-jeng"
    },
    {
      "name": "Shang-Yun Hou",
      "url": "https://patentbrief.org/inventor/shang-yun-hou"
    }
  ],
  "times_cited": 1,
  "tags": [
    "semiconductors",
    "consumer_electronics",
    "telecommunications",
    "software",
    "ai_ml"
  ],
  "abstract": "A chip package may include: a first die; a second die; an underfill disposed between and in physical contact with the first die and the second die; and one or more conductive elements encapsulated in the underfill and coupling the first die and the second die to each other.",
  "url": "https://patentbrief.org/patent/us/9412678/structure-and-method-for-3d-ic-package",
  "markdown_url": "https://patentbrief.org/patent/us/9412678/structure-and-method-for-3d-ic-package/md",
  "google_patents_url": "https://patents.google.com/patent/US9412678",
  "relatedPatents": []
}