# How Asynchronous Buffers Speed Up Non-Volatile Memory Access > This patent describes a non-volatile storage device that uses a special buffer, called an asynchronous FIFO, to quickly deliver data from memory by handling read and write operations with different timing signals and pre-fetching data. - **Patent:** US 9411722 - **Original title:** Asynchronous FIFO buffer for memory access - **Owner:** SanDisk Technologies - **Granted:** 2016 - **Status:** Active - **Times cited:** 7 - **Field:** consumer_electronics, semiconductors, telecommunications, software ## What it does This patent describes a non-volatile storage device, like a flash drive, that uses an asynchronous first-in first-out (FIFO) buffer to manage data flow. The device has a memory array (Claim 1) and a data interface for outputting information. A 'read enable signal' tells the device how to clock data out (Claim 1). The clever part is the asynchronous FIFO buffer, which has separate clock inputs: a 'read clock input' receives the read enable signal, and a 'write clock input' receives a 'write clock' that is a *delayed and asynchronous* version of the read enable signal (Claim 1). This means the buffer can take data from the memory array at one speed and output it at another, independent speed. For example, when you request data from an SSD, the control logic can pre-fetch data into this FIFO buffer *before* your computer even starts asking for it, ensuring it's ready to be clocked out immediately (Claim 6, 8). ## What it does NOT cover - Does not cover synchronous FIFO buffers where read and write operations are tied to the same clock signal. - Does not cover memory systems that do not employ a separate, delayed, and asynchronous write clock for the FIFO buffer. - Does not cover systems that do not pre-fetch data into the FIFO buffer prior to the initial read enable signal. - Does not cover volatile memory types like DRAM, as the claims specifically refer to a 'non-volatile storage device'. - Does not cover data transfer methods that do not use a FIFO buffer as an intermediary between the memory array and the data interface. ## The clever bit The truly novel aspect is using an asynchronous FIFO buffer with a write clock that is a *delayed and asynchronous* version of the read enable signal, combined with pre-fetching data into this buffer. This allows the system to prepare data for output ahead of time, minimizing delays caused by different clock speeds between the memory and the system requesting data. ## Real-world examples 1. Solid-state drives (SSDs) 2. USB flash drives 3. eMMC storage in smartphones and tablets 4. NVMe storage devices 5. Memory controllers in enterprise storage arrays ## Why it matters Modern computing relies heavily on fast access to stored data. Non-volatile storage devices, like SSDs, need to deliver data quickly and efficiently to keep up with processors. This patent improves data delivery by intelligently buffering data, reducing latency and ensuring a smooth flow even when the memory array and the requesting device operate at different speeds. This is crucial for the performance of everything from smartphones to data centers. ## Frequently asked questions ### What does How Asynchronous Buffers Speed Up Non-Volatile Memory Access cover? This patent describes a non-volatile storage device that uses a special buffer, called an asynchronous FIFO, to quickly deliver data from memory by handling read and write operations with different timing signals and pre-fetching data. ### Who owns patent US 9411722? SanDisk Technologies owns this patent, granted in 2016. ### When does this patent expire? This patent is expected to expire on February 28, 2034, when the invention enters the public domain. ### What is patent US 9411722 cited by? This patent has been cited by 7 later patents that build on its ideas. ### What problem does this patent solve? Modern computing relies heavily on fast access to stored data. Non-volatile storage devices, like SSDs, need to deliver data quickly and efficiently to keep up with processors. This patent improves data delivery by intelligently buffering data, reducing latency and ensuring a smooth flow even when the memory array and the requesting device operate at different speeds. This is crucial for the performance of everything from smartphones to data centers. ### What does this patent NOT cover? Does not cover synchronous FIFO buffers where read and write operations are tied to the same clock signal. **Full plain-English explainer:** https://patentbrief.org/patent/us/9411722/asynchronous-fifo-buffer-for-memory-access **Original patent:** https://patents.google.com/patent/US9411722 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How Devices Use 'Credits' to Manage Data Flow to Storage](https://patentbrief.org/patent/us/11593031/operating-method-of-host-device-and-storage-device-using-credit) — This patent describes a system where a main device and a storage device use a 'credit' system to efficiently manage the flow of commands and responses, preventing either side from being overwhelmed with too much data. - [How NAND Flash Memory Adjusts to Cold Temperatures](https://patentbrief.org/patent/us/10019188/storage-devices-memory-systems-and-operating-methods-to-suppress-operating-error) — This patent describes a method for NAND flash memory systems to prevent errors by automatically adjusting their operating conditions, like data speed or voltage, when the temperature drops too low. - [How Multi-Level Cell Memory Stores More Data in Less Space](https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system) — Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming. - [How IBM's Storage Controllers Keep Data Backups in the Right Order](https://patentbrief.org/patent/us/5682513/cache-queue-entry-linking-for-dasd-record-updates) — A method for storage controllers to track and sequence data updates in a specific order, ensuring that remote backups remain consistent with the original data during a system failure. - [How to Prepare 3D Flash Memory for Use](https://patentbrief.org/patent/us/9685235/method-of-initializing-3d-non-volatile-memory-device) — This patent describes a method for setting up a 3D non-volatile memory chip, like those in SSDs, by precisely programming control transistors, including a special "dummy" one, to make sure the memory works correctly.