{
  "patent_number": "US 9411722",
  "country": "US",
  "title": "How Asynchronous Buffers Speed Up Non-Volatile Memory Access",
  "original_title": "Asynchronous FIFO buffer for memory access",
  "summary": "This patent describes a non-volatile storage device that uses a special buffer, called an asynchronous FIFO, to quickly deliver data from memory by handling read and write operations with different timing signals and pre-fetching data.",
  "what_it_does": "This patent describes a non-volatile storage device, like a flash drive, that uses an asynchronous first-in first-out (FIFO) buffer to manage data flow. The device has a memory array (Claim 1) and a data interface for outputting information. A 'read enable signal' tells the device how to clock data out (Claim 1). The clever part is the asynchronous FIFO buffer, which has separate clock inputs: a 'read clock input' receives the read enable signal, and a 'write clock input' receives a 'write clock' that is a *delayed and asynchronous* version of the read enable signal (Claim 1). This means the buffer can take data from the memory array at one speed and output it at another, independent speed. For example, when you request data from an SSD, the control logic can pre-fetch data into this FIFO buffer *before* your computer even starts asking for it, ensuring it's ready to be clocked out immediately (Claim 6, 8).",
  "what_it_does_not_cover": [
    "Does not cover synchronous FIFO buffers where read and write operations are tied to the same clock signal.",
    "Does not cover memory systems that do not employ a separate, delayed, and asynchronous write clock for the FIFO buffer.",
    "Does not cover systems that do not pre-fetch data into the FIFO buffer prior to the initial read enable signal.",
    "Does not cover volatile memory types like DRAM, as the claims specifically refer to a 'non-volatile storage device'.",
    "Does not cover data transfer methods that do not use a FIFO buffer as an intermediary between the memory array and the data interface."
  ],
  "filed": "2014-02-28",
  "granted": "2016-08-09",
  "expires": "2034-02-28",
  "status": "active",
  "holder": "SanDisk Technologies",
  "holder_url": "https://patentbrief.org/company/sandisk-technologies",
  "inventors": [
    {
      "name": "Kian-Chin Alex Yap",
      "url": "https://patentbrief.org/inventor/kian-chin-alex-yap"
    }
  ],
  "times_cited": 7,
  "tags": [
    "consumer_electronics",
    "semiconductors",
    "telecommunications",
    "software"
  ],
  "abstract": "An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.",
  "url": "https://patentbrief.org/patent/us/9411722/asynchronous-fifo-buffer-for-memory-access",
  "markdown_url": "https://patentbrief.org/patent/us/9411722/asynchronous-fifo-buffer-for-memory-access/md",
  "google_patents_url": "https://patents.google.com/patent/US9411722",
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}