# How 3D Memory Chips Fix Tiny Flaws to Keep Working > Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. - **Patent:** US 9263111 - **Original title:** Sub-block disabling in 3D memory - **Owner:** Micron Technology - **Granted:** 2016 - **Status:** Active - **Times cited:** 2 - **Field:** semiconductors, consumer_electronics, telecommunications, software, data_storage ## What it does This patent describes a system and method for selectively disabling small, defective parts of a 3D memory chip, called "sub-blocks," to improve manufacturing yield and device longevity. The apparatus includes a "sub-block disabling circuit" (Claim 1) that stores the addresses of known defective sub-blocks. When the memory receives a request for an address, this circuit checks if the requested address matches a stored defective one. If there's a match, the circuit disables access to that specific sub-block, for example, by deactivating its "drain select gate (SGD) driver" (Claim 2). The patent also covers methods where, if a "threshold number" of sub-blocks in a larger "block" are defective, the entire block might be disabled (Claim 9), or only the individual defective sub-blocks if the count is below the threshold (Claim 13). For example, if a tiny section of a 3D NAND flash chip fails during manufacturing, this system can mark that specific sub-block as unusable, allowing the rest of the chip to function normally. ## What it does NOT cover - Does not cover disabling entire memory blocks unless a specific threshold of sub-block defects within that block is met (Claim 9). - Does not cover memory devices that are not organized into "blocks" containing "two or more sub-blocks" (Claim 1). - Does not cover memory repair mechanisms that physically re-route data to redundant memory cells instead of just disabling access. - Does not cover disabling defective memory cells at a granularity finer than a "sub-block" (Claim 1). - Does not cover disabling sub-blocks in a 2D memory architecture, as it specifically mentions "three-dimensional NOT AND (NAND) memory device" (Claim 6) and "different tier of a semiconductor construction" (Claim 4). ## The clever bit The novelty lies in the granular, address-based disabling of specific "sub-blocks" within a 3D memory structure, rather than just whole blocks or relying on more complex physical remapping. By using a content-addressable memory (CAM) to quickly identify and disable defective sub-blocks, the system can efficiently bypass small flaws without impacting the performance of the rest of the memory. ## Real-world examples 1. Solid-state drives (SSDs) 2. USB flash drives 3. Memory cards (SD cards, microSD cards) 4. Embedded flash memory in smartphones and tablets 5. Enterprise storage arrays 6. Data center storage ## Why it matters Modern 3D NAND flash memory chips are incredibly complex, stacking billions of memory cells in layers. Manufacturing defects are inevitable. This patent provides a crucial mechanism for salvaging chips with minor flaws, significantly improving manufacturing yield and reducing waste. By allowing memory devices to operate even with some defective parts, it helps lower costs and increase the availability of high-capacity storage solutions. This approach is fundamental to the economic viability of large-scale 3D NAND production. ## Frequently asked questions ### What does How 3D Memory Chips Fix Tiny Flaws to Keep Working cover? Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. ### Who owns patent US 9263111? Micron Technology owns this patent, granted in 2016. ### When does this patent expire? This patent is expected to expire on April 9, 2035, when the invention enters the public domain. ### What is patent US 9263111 cited by? This patent has been cited by 2 later patents that build on its ideas. ### What problem does this patent solve? Modern 3D NAND flash memory chips are incredibly complex, stacking billions of memory cells in layers. Manufacturing defects are inevitable. This patent provides a crucial mechanism for salvaging chips with minor flaws, significantly improving manufacturing yield and reducing waste. By allowing memory devices to operate even with some defective parts, it helps lower costs and increase the availability of high-capacity storage solutions. This approach is fundamental to the economic viability of large-scale 3D NAND production. ### What does this patent NOT cover? Does not cover disabling entire memory blocks unless a specific threshold of sub-block defects within that block is met (Claim 9). **Full plain-English explainer:** https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory **Original patent:** https://patents.google.com/patent/US9263111 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How a Special Memory Chip Helps Fix Broken 3D NAND Storage](https://patentbrief.org/patent/us/12450117/firmware-repair-for-three-dimensional-nand-memory) — This patent describes a special content addressable memory (CAM) system that quickly finds and reroutes around defective memory locations in 3D NAND storage using multiple processing units at once. - [How to Prepare 3D Flash Memory for Use](https://patentbrief.org/patent/us/9685235/method-of-initializing-3d-non-volatile-memory-device) — This patent describes a method for setting up a 3D non-volatile memory chip, like those in SSDs, by precisely programming control transistors, including a special "dummy" one, to make sure the memory works correctly. - [How to Precisely Erase Data in 3D NAND Flash Memory](https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory) — This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed. - [How to Program 3D Layered Memory Chips More Precisely](https://patentbrief.org/patent/us/9947413/method-of-initializing-and-programming-3d-non-volatile-memory-device) — This patent describes a method for precisely programming the control transistors and memory cells in advanced 3D non-volatile memory chips, ensuring reliable data storage in stacked layers. - [How Multi-Level Cell Memory Stores More Data in Less Space](https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system) — Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming.