{
  "patent_number": "US 9263111",
  "country": "US",
  "title": "How 3D Memory Chips Fix Tiny Flaws to Keep Working",
  "original_title": "Sub-block disabling in 3D memory",
  "summary": "Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip.",
  "what_it_does": "This patent describes a system and method for selectively disabling small, defective parts of a 3D memory chip, called \"sub-blocks,\" to improve manufacturing yield and device longevity. The apparatus includes a \"sub-block disabling circuit\" (Claim 1) that stores the addresses of known defective sub-blocks. When the memory receives a request for an address, this circuit checks if the requested address matches a stored defective one. If there's a match, the circuit disables access to that specific sub-block, for example, by deactivating its \"drain select gate (SGD) driver\" (Claim 2). The patent also covers methods where, if a \"threshold number\" of sub-blocks in a larger \"block\" are defective, the entire block might be disabled (Claim 9), or only the individual defective sub-blocks if the count is below the threshold (Claim 13). For example, if a tiny section of a 3D NAND flash chip fails during manufacturing, this system can mark that specific sub-block as unusable, allowing the rest of the chip to function normally.",
  "what_it_does_not_cover": [
    "Does not cover disabling entire memory blocks unless a specific threshold of sub-block defects within that block is met (Claim 9).",
    "Does not cover memory devices that are not organized into \"blocks\" containing \"two or more sub-blocks\" (Claim 1).",
    "Does not cover memory repair mechanisms that physically re-route data to redundant memory cells instead of just disabling access.",
    "Does not cover disabling defective memory cells at a granularity finer than a \"sub-block\" (Claim 1).",
    "Does not cover disabling sub-blocks in a 2D memory architecture, as it specifically mentions \"three-dimensional NOT AND (NAND) memory device\" (Claim 6) and \"different tier of a semiconductor construction\" (Claim 4)."
  ],
  "filed": "2015-04-09",
  "granted": "2016-02-16",
  "expires": "2035-04-09",
  "status": "active",
  "holder": "Micron Technology",
  "holder_url": "https://patentbrief.org/company/micron-technology",
  "inventors": [
    {
      "name": "Chang Wan Ha",
      "url": "https://patentbrief.org/inventor/chang-wan-ha"
    }
  ],
  "times_cited": 2,
  "tags": [
    "semiconductors",
    "consumer_electronics",
    "telecommunications",
    "software",
    "data_storage"
  ],
  "abstract": "Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.",
  "url": "https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory",
  "markdown_url": "https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory/md",
  "google_patents_url": "https://patents.google.com/patent/US9263111",
  "relatedPatents": [
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      "countryCode": "US",
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}