# How Chips Are Stacked and Wired in Tiny Phone Parts > MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones. - **Patent:** US 8310051 - **Original title:** Package-on-package with fan-out WLCSP - **Owner:** MediaTek - **Granted:** 2012 - **Status:** Active - **Times cited:** 14 - **Field:** consumer_electronics, telecommunications, semiconductors, software ## What it does This patent describes a way to build a "package-on-package" (PoP) or "system-in-package" (SiP) that stacks different types of computer chips efficiently. It uses a "package carrier" (like a small circuit board) where a main "semiconductor die" (a chip, like a processor) is attached face-down (Claim 1). Between this chip and the carrier is a "rewiring laminate structure" (Claim 1) that takes the tiny electrical connections from the chip's surface and "re-routes" them to "fan-out bond pads" (Claim 5) that extend beyond the edge of the chip (Claim 1). This makes the connections easier to access. On top of this, another "IC package" (like a memory chip) is mounted on the same carrier, partially overlapping the first chip (Claim 1). This stacking allows multiple chips to fit into a very small area. For example, a phone's baseband chip could be the bottom die, with a DRAM chip stacked above it (Claim 7). ## What it does NOT cover - Does not cover chip stacking where the upper IC package directly touches the lower semiconductor die (Claim 2). - Does not cover arrangements where the re-routed metal layer does not extend beyond the edge of the semiconductor die (Claim 1). - Does not cover packages where the IC package and the semiconductor die are not at least partially overlapped (Claim 1). - Does not cover systems where the rewiring laminate structure is absent, or where connections are made directly from the die's contact pads without re-routing (Claim 1, 5). ## The clever bit The novelty lies in combining a "package-on-package" structure with a "fan-out wafer level chip scale package" (WLCSP) for the bottom die. This "rewiring laminate structure" (Claim 1) extends connections beyond the die's edge (Claim 1), allowing for more connection points and easier integration with the stacked IC package, all while keeping the overall footprint small. ## Real-world examples 1. Smartphones 2. Wearable devices 3. Tablet computers 4. Internet of Things (IoT) devices 5. System-in-package (SiP) modules ## Why it matters This packaging method helps make electronic devices smaller and more powerful by allowing different chips to be stacked closely together. By using a "fan-out" wiring technique, it creates more connection points around the chip, which can improve electrical performance and reduce the overall size of the component. This is crucial for compact devices like smartphones and wearables that need many functions in a tiny space. ## Frequently asked questions ### What does How Chips Are Stacked and Wired in Tiny Phone Parts cover? MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones. ### Who owns patent US 8310051? MediaTek owns this patent, granted in 2012. ### When does this patent expire? This patent is expected to expire on October 25, 2031, when the invention enters the public domain. ### What is patent US 8310051 cited by? This patent has been cited by 14 later patents that build on its ideas. ### What problem does this patent solve? This packaging method helps make electronic devices smaller and more powerful by allowing different chips to be stacked closely together. By using a "fan-out" wiring technique, it creates more connection points around the chip, which can improve electrical performance and reduce the overall size of the component. This is crucial for compact devices like smartphones and wearables that need many functions in a tiny space. ### What does this patent NOT cover? Does not cover chip stacking where the upper IC package directly touches the lower semiconductor die (Claim 2). **Full plain-English explainer:** https://patentbrief.org/patent/us/8310051/package-on-package-with-fan-out-wlcsp **Original patent:** https://patents.google.com/patent/US8310051 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How to Stack Computer Chips on a Wafer for Smaller Devices](https://patentbrief.org/patent/us/7824959/wafer-level-stack-structure-for-system-in-package-and-method-thereof) — This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package. - [Stacking Chips with Light-Guiding Plastic Wires](https://patentbrief.org/patent/us/12181722/structures-and-process-flow-for-integrated-photonic-electric-ic-package-by-using) — TSMC's patent describes a method for building advanced chip packages that combine electrical and light-based circuits using polymer waveguides and an integrated fan-out redistribution layer for faster communication. - [How Chips Get Both Light and Electricity on a Special Glass Base](https://patentbrief.org/patent/us/12326604/integrated-circuit-packages-having-electrical-and-optical-connectivity-and-metho) — This patent describes a way to build computer chip packages using a special glass base that can carry both electrical signals and light signals, making chips faster and more efficient. - [How Rohm Designs Compact Semiconductor Packages for Better Heat Management](https://patentbrief.org/patent/us/RE49912/rotomolded-cooler) — A semiconductor packaging design by Rohm that arranges multiple chips and specific lead terminals to optimize space and thermal performance in electronic devices. - [How to Embed Tiny Optical Components Directly into Circuit Boards](https://patentbrief.org/patent/us/RE50510/gemini-bard) — A design for embedding light-emitting components and light-guiding paths directly into the layers of a circuit board to make devices smaller and more efficient.