# How to Stack Computer Chips on a Wafer for Smaller Devices > This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package. - **Patent:** US 7824959 - **Original title:** Wafer level stack structure for system-in-package and method thereof - **Owner:** Samsung Electronics Co - **Granted:** 2010 - **Status:** Active - **Times cited:** 3 - **Field:** semiconductors, consumer_electronics, telecommunications, software ## What it does This patent details a method for creating a stacked chip structure at the wafer level. It involves forming a first wafer with multiple 'first device chips,' each having an active 'first device region' and 'input/output (I/O) pads' within that region (Claim 1). Separately, a second wafer is formed with 'second device chips,' each having a 'second device region,' a 'second peripheral region' around it, and 'I/O pads' in its device region (Claim 1). A key aspect is that while the overall size of the first and second device chips is approximately equal, their active device regions are different sizes (Claim 1). For example, a memory chip (first device) could be stacked directly onto a logic chip (second device) while both are still part of their respective wafers. The two wafers are then stacked and connected, often using tiny conductive 'vias' and 'connection bumps' (Claims 7, 11) that might be rerouted on the second chip (Claim 10). After stacking, the combined wafers can be cut into individual chip stacks (Claim 12). ## What it does NOT cover - Does not cover stacking individual chips after they have been cut from their wafers, as it specifically describes stacking entire wafers. - Does not cover stacking chips where the overall dimensions of the first and second chips are significantly different, as they must be 'approximately equal in size' (Claim 1). - Does not cover stacking chips where the active functional areas ('device regions') are the same size, as they must have 'a different size' (Claim 1). - Does not cover designs where the input/output pads are located entirely outside the active 'device region' of the chip, as they are specified to be 'in the first device region' and 'in the second device region' (Claim 1). - Does not cover methods that do not involve a 'second peripheral region surrounding the second device region' (Claim 1). ## The clever bit The novelty lies in the specific configuration for wafer-level stacking: it allows chips of roughly the same overall dimensions but with different active functional areas to be stacked and connected efficiently. This is managed by using a 'peripheral region' on one chip to accommodate the size difference in the active areas while maintaining overall chip alignment for wafer-level processing. ## Real-world examples 1. Memory-on-logic chip stacks in smartphones 2. Multi-chip modules for compact electronics 3. System-in-Package (SiP) solutions in wearables 4. 3D stacked integrated circuits in high-performance computing 5. Image sensors with stacked processing logic ## Why it matters This patent contributes to the field of advanced semiconductor packaging, specifically for creating System-in-Package (SiP) solutions. By stacking chips at the wafer level, manufacturers can create much smaller, faster, and more power-efficient electronic components. This approach reduces manufacturing costs and improves performance compared to stacking individual chips, which is vital for compact devices like smartphones and wearables. ## Frequently asked questions ### What does How to Stack Computer Chips on a Wafer for Smaller Devices cover? This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package. ### Who owns patent US 7824959? Samsung Electronics Co owns this patent, granted in 2010. ### When does this patent expire? This patent is expected to expire on March 28, 2027, when the invention enters the public domain. ### What is patent US 7824959 cited by? This patent has been cited by 3 later patents that build on its ideas. ### What problem does this patent solve? This patent contributes to the field of advanced semiconductor packaging, specifically for creating System-in-Package (SiP) solutions. By stacking chips at the wafer level, manufacturers can create much smaller, faster, and more power-efficient electronic components. This approach reduces manufacturing costs and improves performance compared to stacking individual chips, which is vital for compact devices like smartphones and wearables. ### What does this patent NOT cover? Does not cover stacking individual chips after they have been cut from their wafers, as it specifically describes stacking entire wafers. **Full plain-English explainer:** https://patentbrief.org/patent/us/7824959/wafer-level-stack-structure-for-system-in-package-and-method-thereof **Original patent:** https://patents.google.com/patent/US7824959 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How Chips Are Stacked and Wired in Tiny Phone Parts](https://patentbrief.org/patent/us/8310051/package-on-package-with-fan-out-wlcsp) — MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones. - [Stacking Chips with Light-Guiding Plastic Wires](https://patentbrief.org/patent/us/12181722/structures-and-process-flow-for-integrated-photonic-electric-ic-package-by-using) — TSMC's patent describes a method for building advanced chip packages that combine electrical and light-based circuits using polymer waveguides and an integrated fan-out redistribution layer for faster communication. - [How Chips Get Both Light and Electricity on a Special Glass Base](https://patentbrief.org/patent/us/12326604/integrated-circuit-packages-having-electrical-and-optical-connectivity-and-metho) — This patent describes a way to build computer chip packages using a special glass base that can carry both electrical signals and light signals, making chips faster and more efficient. - [Attaching Flexible Circuits with Light Sensors to a Chip](https://patentbrief.org/patent/us/9055681/method-for-attaching-a-flexible-structure-to-a-device-and-a-device-having-a-flex) — This patent describes a method and device for attaching a bendable circuit, which includes light-sensing or light-emitting components, onto a main chip, allowing light to pass through a hole in the chip to reach the flexible part. - [Combining Sealed and Exposed Sensors on One Microchip](https://patentbrief.org/patent/us/8387464/laterally-integrated-mems-sensor-device-with-multi-stimulus-sensing) — This patent describes a microchip design that integrates multiple tiny sensors on the same side, where one sensor is exposed to the outside world through a backside hole while others remain protected by a sealed cap.