{
  "patent_number": "US 7824959",
  "country": "US",
  "title": "How to Stack Computer Chips on a Wafer for Smaller Devices",
  "original_title": "Wafer level stack structure for system-in-package and method thereof",
  "summary": "This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package.",
  "what_it_does": "This patent details a method for creating a stacked chip structure at the wafer level. It involves forming a first wafer with multiple 'first device chips,' each having an active 'first device region' and 'input/output (I/O) pads' within that region (Claim 1). Separately, a second wafer is formed with 'second device chips,' each having a 'second device region,' a 'second peripheral region' around it, and 'I/O pads' in its device region (Claim 1). A key aspect is that while the overall size of the first and second device chips is approximately equal, their active device regions are different sizes (Claim 1). For example, a memory chip (first device) could be stacked directly onto a logic chip (second device) while both are still part of their respective wafers. The two wafers are then stacked and connected, often using tiny conductive 'vias' and 'connection bumps' (Claims 7, 11) that might be rerouted on the second chip (Claim 10). After stacking, the combined wafers can be cut into individual chip stacks (Claim 12).",
  "what_it_does_not_cover": [
    "Does not cover stacking individual chips after they have been cut from their wafers, as it specifically describes stacking entire wafers.",
    "Does not cover stacking chips where the overall dimensions of the first and second chips are significantly different, as they must be 'approximately equal in size' (Claim 1).",
    "Does not cover stacking chips where the active functional areas ('device regions') are the same size, as they must have 'a different size' (Claim 1).",
    "Does not cover designs where the input/output pads are located entirely outside the active 'device region' of the chip, as they are specified to be 'in the first device region' and 'in the second device region' (Claim 1).",
    "Does not cover methods that do not involve a 'second peripheral region surrounding the second device region' (Claim 1)."
  ],
  "filed": "2007-03-28",
  "granted": "2010-11-02",
  "expires": "2027-03-28",
  "status": "active",
  "holder": "Samsung Electronics Co",
  "holder_url": "https://patentbrief.org/company/samsung-electronics-co",
  "inventors": [
    {
      "name": "Kang-Wook Lee",
      "url": "https://patentbrief.org/inventor/kang-wook-lee"
    },
    {
      "name": "Se-Yong Oh",
      "url": "https://patentbrief.org/inventor/se-yong-oh"
    },
    {
      "name": "Gu-Sung Kim",
      "url": "https://patentbrief.org/inventor/gu-sung-kim"
    },
    {
      "name": "Young-hee Song",
      "url": "https://patentbrief.org/inventor/young-hee-song"
    }
  ],
  "times_cited": 3,
  "tags": [
    "semiconductors",
    "consumer_electronics",
    "telecommunications",
    "software"
  ],
  "abstract": "A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.",
  "url": "https://patentbrief.org/patent/us/7824959/wafer-level-stack-structure-for-system-in-package-and-method-thereof",
  "markdown_url": "https://patentbrief.org/patent/us/7824959/wafer-level-stack-structure-for-system-in-package-and-method-thereof/md",
  "google_patents_url": "https://patents.google.com/patent/US7824959",
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}