# How Intel's Memory Hub Manages Graphics Data Across Different Memory Types > A hardware design for a computer memory hub that lets a processor treat different types of memory as one unified space for graphics tasks. - **Patent:** US 6362826 - **Original title:** Method and apparatus for implementing dynamic display memory - **Owner:** Intel Corp - **Granted:** 2002 - **Status:** Public domain (expired) - **Times cited:** 25 - **Field:** semiconductors, consumer_electronics ## What it does This patent describes a memory control hub that acts as a traffic cop between a computer's main processor and its memory. When the processor needs to access graphics data, the hub checks if the data is a graphics operand. If it is, the hub uses a translation table to map the processor's virtual address to the actual physical location of the data, which might be in main system memory or dedicated graphics memory. This allows the system to seamlessly move or store graphics data across two different memory pools while keeping the processor's job simple. ## What it does NOT cover - Does not cover software-only methods for memory management that lack a hardware memory control hub. - Does not cover systems that only use a single unified memory pool without a translation table mechanism. - Does not cover methods of graphics rendering or image processing algorithms themselves. ## The clever bit The invention uses a translation table and fence registers to reorder memory addresses on the fly, effectively hiding the complexity of physical memory location from the CPU while optimizing access patterns for the graphics device. ## Real-world examples 1. Intel integrated graphics chipsets from the early 2000s 2. Unified Memory Architecture (UMA) implementations in desktop PCs ## Why it matters This technology was crucial during the transition to integrated graphics architectures where the line between system RAM and dedicated video memory began to blur. By allowing the CPU to manage graphics memory dynamically, it helped improve performance in early 2000s PC architectures, specifically those using Intel's chipset designs. ## Frequently asked questions ### What does How Intel's Memory Hub Manages Graphics Data Across Different Memory Types cover? A hardware design for a computer memory hub that lets a processor treat different types of memory as one unified space for graphics tasks. ### Who owns patent US 6362826? Intel Corp owns this patent, granted in 2002. ### When does this patent expire? This patent has expired and is now in the public domain — anyone can use the invention freely. ### What is patent US 6362826 cited by? This patent has been cited by 25 later patents that build on its ideas. ### What problem does this patent solve? This technology was crucial during the transition to integrated graphics architectures where the line between system RAM and dedicated video memory began to blur. By allowing the CPU to manage graphics memory dynamically, it helped improve performance in early 2000s PC architectures, specifically those using Intel's chipset designs. ### What does this patent NOT cover? Does not cover software-only methods for memory management that lack a hardware memory control hub. **Full plain-English explainer:** https://patentbrief.org/patent/us/6362826/method-and-apparatus-for-implementing-dynamic-display-memory **Original patent:** https://patents.google.com/patent/US6362826 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How Graphics Processors Switch Between Different Tasks Efficiently](https://patentbrief.org/patent/us/7512773/context-switching-using-halt-sequencing-protocol) — A method for graphics chips to pause and swap between different programs or tasks without waiting for every single part of the processor to finish its current job. - [How to Save Memory Power by Grouping Error-Correction Data](https://patentbrief.org/patent/us/12321234/raptor-2) — A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one. - [How 3D Memory Chips Fix Tiny Flaws to Keep Working](https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory) — Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. - [Making Memory Chips Faster by Splitting Internal Wires](https://patentbrief.org/patent/us/12740066/split-memory-array-to-reduce-bit-line-capacitance) — This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access. - [How Devices Use 'Credits' to Manage Data Flow to Storage](https://patentbrief.org/patent/us/11593031/operating-method-of-host-device-and-storage-device-using-credit) — This patent describes a system where a main device and a storage device use a 'credit' system to efficiently manage the flow of commands and responses, preventing either side from being overwhelmed with too much data.