{
  "patent_number": "US 5903495",
  "country": "US",
  "title": "How Multi-Level Cell Memory Stores More Data in Less Space",
  "original_title": "Semiconductor device and memory system",
  "summary": "Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming.",
  "what_it_does": "This patent details a technique for Multi-Level Cell (MLC) flash memory, where each memory cell can store more than one bit of data by using multiple distinct voltage thresholds. It describes a two-step programming process where the voltage bias applied to the cell increases in specific, controlled increments (ΔVpp1 and ΔVpp2). By using a smaller step-up value for the first programming phase and a larger one for the second, the device ensures the threshold voltage distributions remain accurate and distinct, allowing the cell to reliably hold values like '1', '2', or '3'.",
  "what_it_does_not_cover": [
    "Does not cover Single-Level Cell (SLC) memory where each cell stores only one bit.",
    "Does not cover memory architectures that do not use stepwise bias increases for programming.",
    "Does not cover the physical manufacturing process of the silicon wafers themselves.",
    "Does not cover the specific error-correction algorithms used to read the data."
  ],
  "filed": "1997-03-17",
  "granted": "1999-05-11",
  "expires": "2017-03-17",
  "status": "expired",
  "holder": "Toshiba Corp",
  "holder_url": "https://patentbrief.org/company/toshiba-corp",
  "inventors": [
    {
      "name": "Tomoharu Tanaka",
      "url": "https://patentbrief.org/inventor/tomoharu-tanaka"
    },
    {
      "name": "Ken Takeuchi",
      "url": "https://patentbrief.org/inventor/ken-takeuchi"
    }
  ],
  "times_cited": 326,
  "tags": [
    "semiconductors",
    "consumer_electronics"
  ],
  "abstract": "A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data items read from said memory cells, wherein data items read from said memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits, during data-reading operation.",
  "url": "https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system",
  "markdown_url": "https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system/md",
  "google_patents_url": "https://patents.google.com/patent/US5903495",
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}