# How Xilinx Chips Quickly Check If Memory Is Completely Erased > A method for programmable chips to instantly verify that all memory cells are wiped clean using a simple, high-speed logic gate circuit. - **Patent:** US 5561631 - **Original title:** High-speed minimal logic self blank checking method for programmable logic device - **Owner:** Xilinx Inc - **Granted:** 1996 - **Status:** Public domain (expired) - **Times cited:** 5 - **Field:** semiconductors, mechanical ## What it does This patent describes a hardware circuit designed to verify if memory cells in a programmable logic device (PLD) are fully erased. It uses an n-input NOR gate formed by NMOS transistors connected to sense amplifiers. When a wordline is activated, the circuit checks all memory cells on that line simultaneously. If any single cell is not fully erased, its sense amplifier outputs a high signal, which turns on an NMOS transistor and pulls the common output node low, signaling that the device is not yet clean. ## What it does NOT cover - Does not cover software-based verification methods that check memory cells one by one. - Does not cover memory architectures that do not use sense amplifiers as input sources for the gate. - Does not cover non-volatile memory technologies that do not utilize wordline-based addressing. ## The clever bit Instead of reading each cell individually, the circuit uses the physical properties of a NOR gate to perform a parallel 'all-or-nothing' check, where a single un-erased cell immediately forces the output to a 'not erased' state. ## Real-world examples 1. Xilinx FPGA configuration memory 2. Programmable logic device (PLD) erasure cycles 3. High-density memory array testing ## Why it matters Before this, checking if a large programmable chip was fully erased could be a slow, iterative process. By implementing this logic gate directly into the hardware, Xilinx made the erasure verification process nearly instantaneous, which is critical for manufacturing efficiency and device reliability in field-programmable gate arrays (FPGAs). ## Frequently asked questions ### What does How Xilinx Chips Quickly Check If Memory Is Completely Erased cover? A method for programmable chips to instantly verify that all memory cells are wiped clean using a simple, high-speed logic gate circuit. ### Who owns patent US 5561631? Xilinx Inc owns this patent, granted in 1996. ### When does this patent expire? This patent has expired and is now in the public domain — anyone can use the invention freely. ### What is patent US 5561631 cited by? This patent has been cited by 5 later patents that build on its ideas. ### What problem does this patent solve? Before this, checking if a large programmable chip was fully erased could be a slow, iterative process. By implementing this logic gate directly into the hardware, Xilinx made the erasure verification process nearly instantaneous, which is critical for manufacturing efficiency and device reliability in field-programmable gate arrays (FPGAs). ### What does this patent NOT cover? Does not cover software-based verification methods that check memory cells one by one. **Full plain-English explainer:** https://patentbrief.org/patent/us/5561631/high-speed-minimal-logic-self-blank-checking-method-for-programmable-logic-device **Original patent:** https://patents.google.com/patent/US5561631 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How to Precisely Erase Data in 3D NAND Flash Memory](https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory) — This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed. - [How Flash Memory Cells Use an Erase Gate to Clear Data](https://patentbrief.org/patent/us/4531203/nand-flash-memory) — This 1985 patent describes the foundational structure of flash memory, introducing an 'erase gate' that allows data to be electrically wiped from a memory cell. - [How to Combine FPGA and Non-Volatile Memory Chips in One Package](https://patentbrief.org/patent/us/12737520/non-volatile-programmable-logic-device-based-on-multi-chip-package) — This patent describes a compact chip package that integrates multiple semiconductor chips, specifically an FPGA and a non-volatile memory chip, using precisely dimensioned metal and dielectric layers over a polymer layer for a logic drive. - [Making Memory Chips Faster by Splitting Internal Wires](https://patentbrief.org/patent/us/12740066/split-memory-array-to-reduce-bit-line-capacitance) — This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access. - [How 3D Memory Chips Fix Tiny Flaws to Keep Working](https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory) — Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip.