# Training AI Chips Using Memristor Crossbars Directly On-Chip > This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently. - **Patent:** US 20230409893 - **Original title:** On-chip training of memristor crossbar neuromorphic processing systems - **Owner:** University of Dayton - **Status:** Active - **Times cited:** 0 - **Field:** semiconductors, ai_ml, consumer_electronics, telecommunications, automotive ## What it does This patent describes an analog neuromorphic circuit designed for on-chip training of artificial intelligence. It uses a grid of 'resistive memories' (like memristors) that can change how much they resist electrical current. When an 'input voltage signal' goes through these memories, it creates a 'first output voltage signal' (Claim 1). A 'first comparator' then checks this output against a 'desired output signal' and figures out the difference, creating a 'first error signal' (Claim 1). This error signal then travels *backwards* through the *same* resistive memories, generating a 'second output voltage signal' (Claim 1). Finally, a 'resistance adjuster' tweaks the resistance of each memory based on both the error signal and the second output, aiming to make the first output closer to the desired one (Claim 1). For example, if the circuit is trying to recognize a handwritten 'A' but outputs something closer to a 'B', the error signal helps the memristors adjust their internal connections to correctly identify 'A' next time. ## What it does NOT cover - Does not cover neuromorphic circuits that perform training off-chip, requiring data to be sent to a separate processor. - Does not cover systems that use different sets of resistive memories or components for the forward pass and the error back-propagation steps (Claim 6). - Does not cover digital neuromorphic circuits, as the claims specifically refer to an 'analog neuromorphic circuit' (Claim 1). - Does not cover training methods where the resistance adjustment is not based on both a 'first error signal' and a 'second output voltage signal' generated by the backward pass (Claim 1). - Does not cover circuits where the resistive memories are not arranged in a grid configuration with distinct vertical and horizontal neuron groupings for signal and error propagation (Claim 3, 5). ## The clever bit The truly clever part is reusing the *same* set of resistive memories for both the forward pass (processing the input) and the backward pass (propagating the error signal to adjust the memories). This eliminates the need for duplicate hardware, making the on-chip training more compact and energy-efficient. ## Real-world examples 1. Neuromorphic processors for edge AI devices 2. Self-learning sensors 3. AI accelerators for autonomous vehicles 4. Smart home devices with adaptive learning capabilities 5. Robotics with real-time learning ## Why it matters Traditional AI training often happens on powerful computers, then the trained model is put onto a smaller chip for use. This patent aims to allow the training itself to happen directly on the chip, which could make AI devices more efficient, faster, and able to learn new things in real-time without needing to connect to a cloud server. This is crucial for edge AI applications where power and latency are critical. ## Frequently asked questions ### What does Training AI Chips Using Memristor Crossbars Directly On-Chip cover? This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently. ### Who owns patent US 20230409893? This patent is owned by University of Dayton. ### When does this patent expire? This patent is expected to expire on September 5, 2043, when the invention enters the public domain. ### What problem does this patent solve? Traditional AI training often happens on powerful computers, then the trained model is put onto a smaller chip for use. This patent aims to allow the training itself to happen directly on the chip, which could make AI devices more efficient, faster, and able to learn new things in real-time without needing to connect to a cloud server. This is crucial for edge AI applications where power and latency are critical. ### What does this patent NOT cover? Does not cover neuromorphic circuits that perform training off-chip, requiring data to be sent to a separate processor. **Full plain-English explainer:** https://patentbrief.org/patent/us/20230409893/on-chip-training-of-memristor-crossbar-neuromorphic-processing-systems **Original patent:** https://patents.google.com/patent/US20230409893 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How a Memristor Circuit Adjusts AI Network Weights](https://patentbrief.org/patent/us/12056602/circuit-for-calculating-weight-adjustments-of-an-artificial-neural-network-and-a) — This patent describes a specialized electronic circuit that uses memristors to store and adjust the 'weights' of an artificial neural network, making AI calculations more efficient. - [How a Single Electronic Component Can Learn and Process AI Data](https://patentbrief.org/patent/us/10248907/resistive-processing-unit) — This patent describes a tiny electronic component called a resistive processing unit (RPU) that acts like a brain cell in an artificial intelligence network, storing and processing information directly within its changing electrical resistance. - [How Nanoparticles Form Adaptive Neural Network Connections](https://patentbrief.org/patent/us/8156057/adaptive-neural-network-utilizing-nanotechnology-based-components) — This patent describes how to build and strengthen a physical neural network using tiny nanoparticles suspended in a liquid, where electric fields make the connections learn and adapt. - [How to Fix Faulty Memory Cells in AI Chips](https://patentbrief.org/patent/us/10956815/killing-asymmetric-resistive-processing-units-for-neural-network-training) — This patent describes a system that tests individual memory cells in AI chips for uneven behavior and then permanently disables the faulty ones before the chip starts learning, making AI training more efficient. - [How a Chip Uses Memory to Speed Up AI Calculations](https://patentbrief.org/patent/us/11741188/hardware-accelerated-discretized-neural-network) — This patent describes a specialized computer chip that uses non-volatile memory and analog signals to quickly perform calculations for artificial intelligence, especially for neural networks that need to remember past information.