{
  "patent_number": "US 20230409893",
  "country": "US",
  "title": "Training AI Chips Using Memristor Crossbars Directly On-Chip",
  "original_title": "On-chip training of memristor crossbar neuromorphic processing systems",
  "summary": "This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently.",
  "what_it_does": "This patent describes an analog neuromorphic circuit designed for on-chip training of artificial intelligence. It uses a grid of 'resistive memories' (like memristors) that can change how much they resist electrical current. When an 'input voltage signal' goes through these memories, it creates a 'first output voltage signal' (Claim 1). A 'first comparator' then checks this output against a 'desired output signal' and figures out the difference, creating a 'first error signal' (Claim 1). This error signal then travels *backwards* through the *same* resistive memories, generating a 'second output voltage signal' (Claim 1). Finally, a 'resistance adjuster' tweaks the resistance of each memory based on both the error signal and the second output, aiming to make the first output closer to the desired one (Claim 1). For example, if the circuit is trying to recognize a handwritten 'A' but outputs something closer to a 'B', the error signal helps the memristors adjust their internal connections to correctly identify 'A' next time.",
  "what_it_does_not_cover": [
    "Does not cover neuromorphic circuits that perform training off-chip, requiring data to be sent to a separate processor.",
    "Does not cover systems that use different sets of resistive memories or components for the forward pass and the error back-propagation steps (Claim 6).",
    "Does not cover digital neuromorphic circuits, as the claims specifically refer to an 'analog neuromorphic circuit' (Claim 1).",
    "Does not cover training methods where the resistance adjustment is not based on both a 'first error signal' and a 'second output voltage signal' generated by the backward pass (Claim 1).",
    "Does not cover circuits where the resistive memories are not arranged in a grid configuration with distinct vertical and horizontal neuron groupings for signal and error propagation (Claim 3, 5)."
  ],
  "filed": "2023-09-05",
  "granted": null,
  "expires": "2043-09-05",
  "status": "active",
  "holder": "University of Dayton",
  "holder_url": "https://patentbrief.org/company/university-of-dayton",
  "inventors": [
    {
      "name": "Tarek M. Taha",
      "url": "https://patentbrief.org/inventor/tarek-m-taha"
    },
    {
      "name": "Md Raqibul Hasan",
      "url": "https://patentbrief.org/inventor/md-raqibul-hasan"
    },
    {
      "name": "Chris Yakopcic",
      "url": "https://patentbrief.org/inventor/chris-yakopcic"
    }
  ],
  "times_cited": 0,
  "tags": [
    "semiconductors",
    "ai_ml",
    "consumer_electronics",
    "telecommunications",
    "automotive"
  ],
  "abstract": "An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.",
  "url": "https://patentbrief.org/patent/us/20230409893/on-chip-training-of-memristor-crossbar-neuromorphic-processing-systems",
  "markdown_url": "https://patentbrief.org/patent/us/20230409893/on-chip-training-of-memristor-crossbar-neuromorphic-processing-systems/md",
  "google_patents_url": "https://patents.google.com/patent/US20230409893",
  "relatedPatents": [
    {
      "patentNumber": "12056602",
      "countryCode": "US",
      "title": "How a Memristor Circuit Adjusts AI Network Weights",
      "url": "https://patentbrief.org/patent/us/12056602/circuit-for-calculating-weight-adjustments-of-an-artificial-neural-network-and-a"
    },
    {
      "patentNumber": "10248907",
      "countryCode": "US",
      "title": "How a Single Electronic Component Can Learn and Process AI Data",
      "url": "https://patentbrief.org/patent/us/10248907/resistive-processing-unit"
    },
    {
      "patentNumber": "8156057",
      "countryCode": "US",
      "title": "How Nanoparticles Form Adaptive Neural Network Connections",
      "url": "https://patentbrief.org/patent/us/8156057/adaptive-neural-network-utilizing-nanotechnology-based-components"
    },
    {
      "patentNumber": "10956815",
      "countryCode": "US",
      "title": "How to Fix Faulty Memory Cells in AI Chips",
      "url": "https://patentbrief.org/patent/us/10956815/killing-asymmetric-resistive-processing-units-for-neural-network-training"
    },
    {
      "patentNumber": "11741188",
      "countryCode": "US",
      "title": "How a Chip Uses Memory to Speed Up AI Calculations",
      "url": "https://patentbrief.org/patent/us/11741188/hardware-accelerated-discretized-neural-network"
    }
  ]
}